component
DMP4015SSSQ-13
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Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DMP4015SSSQ-13
Diodes Incorporated · MOSFETs · SO-8
DMP4015SSSQ-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET (VDSS -40V, ID up to -10.1A). |
| 2 | S | passive | Source terminal of the P-channel MOSFET, tied in parallel with the other source pins. |
| 3 | S | passive | Source terminal of the P-channel MOSFET, tied in parallel with the other source pins. |
| 4 | G | input | Gate terminal; gate-source voltage rated ±25V, threshold -1.5V to -2.5V. |
| 5 | D | passive | Drain terminal of the P-channel MOSFET, tied in parallel with the other drain pins. |
| 6 | D | passive | Drain terminal of the P-channel MOSFET, tied in parallel with the other drain pins. |
| 7 | D | passive | Drain terminal of the P-channel MOSFET, tied in parallel with the other drain pins. |
| 8 | D | passive | Drain terminal of the P-channel MOSFET; drain-source voltage rated -40V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS | -40 | V | 2 | |||
| Gate-Source Voltage | VGSS | -25 | 25 | V | 2 | ||
| Continuous Drain Current | ID | -9.1 | A | VGS = -10V, steady state, TA = +25°C, Note 5 | 2 | ||
| Continuous Drain Current | ID | -7.2 | A | VGS = -10V, steady state, TA = +70°C, Note 5 | 2 | ||
| Continuous Drain Current | ID | -7.8 | A | VGS = -4.5V, steady state, TA = +25°C, Note 5 | 2 | ||
| Continuous Drain Current | ID | -6.2 | A | VGS = -4.5V, steady state, TA = +70°C, Note 5 | 2 | ||
| Continuous Drain Current | ID | -10.1 | A | VGS = -10V, steady state, TA = +25°C, Note 6 | 2 | ||
| Continuous Drain Current | ID | -8 | A | VGS = -10V, steady state, TA = +70°C, Note 6 | 2 | ||
| Continuous Drain Current | ID | -8.8 | A | VGS = -4.5V, steady state, TA = +25°C, Note 6 | 2 | ||
| Continuous Drain Current | ID | -7 | A | VGS = -4.5V, steady state, TA = +70°C, Note 6 | 2 | ||
| Pulsed Drain Current | IDM | -100 | A | 10μs pulse, duty cycle = 1% | 2 | ||
| Avalanche Current | IAS | -22 | A | Note 7 | 2 | ||
| Avalanche Energy | EAS | 242 | mJ | Note 7 | 2 | ||
| Total Power Dissipation | PD | 1.45 | W | Note 5 | 2 | ||
| Total Power Dissipation | PD | 1.82 | W | Note 6 | 2 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 88 | °C/W | Note 5 | 2 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 70 | °C/W | Note 6 | 2 | ||
| Thermal Resistance, Junction to Case | RθJC | 7.6 | °C/W | Note 6 | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 | ||
| Drain-Source Breakdown Voltage | BVDSS | -40 | V | VGS = 0V, ID = -250μA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -1 | μA | VDS = -40V, VGS = 0V | 2 | ||
| Gate-Source Leakage | IGSS | 100 | nA | VGS = 25V, VDS = 0V | 2 | ||
| Gate Threshold Voltage | VGS(TH) | -1.5 | -2 | -2.5 | V | VDS = VGS, ID = -250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | 7 | 11 | mΩ | VGS = -10V, ID = -9.8A | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 9 | 15 | mΩ | VGS = -4.5V, ID = -9.8A | 2 | |
| Diode Forward Voltage | VSD | -0.7 | -1 | V | VGS = 0V, IS = -1A | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | Terminal Connections: See Diagram Terminals: Finish, Matte Tin Annealed over Copper Leadframe. | 1 |
CAD (KiCad official)
- Symbol:
DMP4015SSSQ-13 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
dmp4015sssq-13-etched.step/dmp4015sssq-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmp4015sssq-13.step/dmp4015sssq-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (7 pp, sha256
3b5c6d008521f533, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DMP4015SSSQ-13
**Diodes Incorporated** · MOSFETs · SO-8
DMP4015SSSQ-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET (VDSS -40V, ID up to -10.1A). |
| 2 | S | passive | Source terminal of the P-channel MOSFET, tied in parallel with the other source pins. |
| 3 | S | passive | Source terminal of the P-channel MOSFET, tied in parallel with the other source pins. |
| 4 | G | input | Gate terminal; gate-source voltage rated ±25V, threshold -1.5V to -2.5V. |
| 5 | D | passive | Drain terminal of the P-channel MOSFET, tied in parallel with the other drain pins. |
| 6 | D | passive | Drain terminal of the P-channel MOSFET, tied in parallel with the other drain pins. |
| 7 | D | passive | Drain terminal of the P-channel MOSFET, tied in parallel with the other drain pins. |
| 8 | D | passive | Drain terminal of the P-channel MOSFET; drain-source voltage rated -40V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS | -40 | | | V | | 2 |
| Gate-Source Voltage | VGSS | -25 | | 25 | V | | 2 |
| Continuous Drain Current | ID | -9.1 | | | A | VGS = -10V, steady state, TA = +25°C, Note 5 | 2 |
| Continuous Drain Current | ID | -7.2 | | | A | VGS = -10V, steady state, TA = +70°C, Note 5 | 2 |
| Continuous Drain Current | ID | -7.8 | | | A | VGS = -4.5V, steady state, TA = +25°C, Note 5 | 2 |
| Continuous Drain Current | ID | -6.2 | | | A | VGS = -4.5V, steady state, TA = +70°C, Note 5 | 2 |
| Continuous Drain Current | ID | -10.1 | | | A | VGS = -10V, steady state, TA = +25°C, Note 6 | 2 |
| Continuous Drain Current | ID | -8 | | | A | VGS = -10V, steady state, TA = +70°C, Note 6 | 2 |
| Continuous Drain Current | ID | -8.8 | | | A | VGS = -4.5V, steady state, TA = +25°C, Note 6 | 2 |
| Continuous Drain Current | ID | -7 | | | A | VGS = -4.5V, steady state, TA = +70°C, Note 6 | 2 |
| Pulsed Drain Current | IDM | -100 | | | A | 10μs pulse, duty cycle = 1% | 2 |
| Avalanche Current | IAS | -22 | | | A | Note 7 | 2 |
| Avalanche Energy | EAS | | | 242 | mJ | Note 7 | 2 |
| Total Power Dissipation | PD | | | 1.45 | W | Note 5 | 2 |
| Total Power Dissipation | PD | | | 1.82 | W | Note 6 | 2 |
| Thermal Resistance, Junction to Ambient | RθJA | | | 88 | °C/W | Note 5 | 2 |
| Thermal Resistance, Junction to Ambient | RθJA | | | 70 | °C/W | Note 6 | 2 |
| Thermal Resistance, Junction to Case | RθJC | | | 7.6 | °C/W | Note 6 | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 | | 150 | °C | | 2 |
| Drain-Source Breakdown Voltage | BVDSS | -40 | | | V | VGS = 0V, ID = -250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | -1 | μA | VDS = -40V, VGS = 0V | 2 |
| Gate-Source Leakage | IGSS | | | 100 | nA | VGS = 25V, VDS = 0V | 2 |
| Gate Threshold Voltage | VGS(TH) | -1.5 | -2 | -2.5 | V | VDS = VGS, ID = -250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 7 | 11 | mΩ | VGS = -10V, ID = -9.8A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 9 | 15 | mΩ | VGS = -4.5V, ID = -9.8A | 2 |
| Diode Forward Voltage | VSD | | -0.7 | -1 | V | VGS = 0V, IS = -1A | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | Terminal Connections: See Diagram Terminals: Finish, Matte Tin Annealed over Copper Leadframe. | 1 |
## CAD (KiCad official)
- Symbol: `DMP4015SSSQ-13`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `dmp4015sssq-13-etched.step` / `dmp4015sssq-13-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmp4015sssq-13.step` / `dmp4015sssq-13.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590907968441970688) (7 pp, sha256 `3b5c6d008521f533`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dmp4015sssq-13-datasheet.pdf)