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DMP3068LVT-13

Diodes Incorporated · MOSFETs · TSOT-26

DMP3068LVT-13 from Diodes Incorporated, in a TSOT-26. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D passive Drain, internally connected to the other drain pins (2, 5, 6); the -30V P-channel drain.
2 D passive Drain, internally connected to the other drain pins (1, 5, 6); the -30V P-channel drain.
3 G input Gate, with a threshold of -0.5V to -1.3V at ID = -250µA and a maximum VGS of ±12V.
4 S passive Source of the P-channel MOSFET.
5 D passive Drain, internally connected to the other drain pins (1, 2, 6); the -30V P-channel drain.
6 D passive Drain, internally connected to the other drain pins (1, 2, 5); the -30V P-channel drain.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package TSOT-26
Category Transistors/Thyristors
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDSS -30 V 2
Gate-Source Voltage VGSS -12 12 V 2
Continuous Drain Current ID -2.8 A VGS = -4.5V, steady state, TA = +25°C 2
Continuous Drain Current ID -2.2 A VGS = -4.5V, steady state, TA = +70°C 2
Maximum Body Diode Forward Current IS -1.6 A Note 6 2
Pulsed Drain Current IDM -20 A 10μs pulse, duty cycle = 1% 2
Total Power Dissipation PD 1.25 W Note 5: FR-4 PCB, 2oz copper, minimum recommended pad layout 2
Thermal Resistance, Junction to Ambient (Steady State) RϴJA 100 °C/W Note 5: FR-4 PCB, 2oz copper, minimum recommended pad layout 2
Total Power Dissipation PD 1.8 W Note 6: FR-4 PCB, 2oz copper, 1inch square copper plate 2
Thermal Resistance, Junction to Ambient (Steady State) RϴJA 70 °C/W Note 6: FR-4 PCB, 2oz copper, 1inch square copper plate 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2
Drain-Source Breakdown Voltage BVDSS -30 V VGS = 0V, ID = -250µA 2
Zero Gate Voltage Drain Current IDSS -1 µA TJ = +25°C, VDS = -30V, VGS = 0V 2
Gate-Source Leakage IGSS -100 100 nA VGS = ±12V, VDS = 0V 2
Gate Threshold Voltage VGS(TH) -0.5 -1.3 V VDS = VGS, ID = -250µA 2
Static Drain-Source On-Resistance RDS(ON) 75 mΩ VGS = -10V, ID = -4.2A 2
Static Drain-Source On-Resistance RDS(ON) 105 mΩ VGS = -4.5V, ID = -4.0A 2
Static Drain-Source On-Resistance RDS(ON) 150 mΩ VGS = -2.5V, ID = -2.0A 2
Diode Forward Voltage VSD -1.2 V VGS = 0V, IS = -1A 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts Copper tin  Terminal Connections: See Diagram  Terminals: Finish, Tin Finish Annealed over Copper Leadframe. 1

CAD (KiCad official)

  • Symbol: DMP3068LVT-13
  • Footprint: Package_TO_SOT_SMD:TSOT-23-6
  • 3D model: TSOT-26 (KiCad packages3D, STEP)
  • 3D model files: dmp3068lvt-13-etched.step / dmp3068lvt-13-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dmp3068lvt-13.step / dmp3068lvt-13.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (7 pp, sha256 bc1326f011f4e2c4, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF