component
DMP3056LSD
Public Made by Adomby adom
Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DMP3056LSD
Diodes Incorporated · MOSFETs · SO-8
DMP3056LSD from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of P-channel MOSFET 1. |
| 2 | G1 | input | Gate of P-channel MOSFET 1, with VGSS rated ±20 V. |
| 3 | S2 | passive | Source of P-channel MOSFET 2. |
| 4 | G2 | input | Gate of P-channel MOSFET 2, with VGSS rated ±20 V. |
| 5 | D2 | passive | Drain of P-channel MOSFET 2, with VDSS rated -30 V. |
| 6 | D2 | passive | Drain of P-channel MOSFET 2, with VDSS rated -30 V, internally tied to pin 5. |
| 7 | D1 | passive | Drain of P-channel MOSFET 1, with VDSS rated -30 V. |
| 8 | D1 | passive | Drain of P-channel MOSFET 1, with VDSS rated -30 V, internally tied to pin 7. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -30 | V | VGS = 0V, ID = -250µA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -1 | µA | VDS = -30V, VGS = 0V | 2 | ||
| Gate-Source Leakage | IGSS | -100 | 100 | nA | VGS = ±20V, VDS = 0V | 2 | |
| Gate-Source Leakage | IGSS | -800 | 800 | nA | VGS = ±25V, VDS = 0V | 2 | |
| Gate Threshold Voltage | VGS(th) | -1 | -1.7 | -2.1 | V | VDS = VGS, ID = -250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | 45 | mΩ | VGS = -10V, ID = -6.0A | 2 | ||
| Static Drain-Source On-Resistance | RDS(ON) | 65 | mΩ | VGS = -4.5V, ID = -5.0A | 2 | ||
| Diode Forward Voltage | VSD | -0.5 | -1.2 | V | VGS = 0V, IS = -1.7A | 2 | |
| Drain-Source Voltage | VDSS | -30 | V | TA = +25°C | 2 | ||
| Gate-Source Voltage | VGSS | -20 | 20 | V | TA = +25°C | 2 | |
| Drain Current | ID | -6.9 | A | Steady state, TA = +25°C | 2 | ||
| Drain Current | ID | -5.8 | A | Steady state, TA = +70°C | 2 | ||
| Pulsed Drain Current | IDM | -24 | A | Pulse width ≤10μS, Duty Cycle ≤1% | 2 | ||
| Total Power Dissipation | PD | 2.5 | W | Device mounted on 2 oz. 1" x 1" Cu pads on 2" x 2" FR-4 PCB | 2 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 50 | °C/W | Device mounted on 2 oz. 1" x 1" Cu pads on 2" x 2" FR-4 PCB | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 | ||
| Forward Transconductance | gfs | 8 | S | VDS = -10V, ID = -5.3A | 2 | ||
| Input Capacitance | Ciss | 722 | pF | VDS = -25V, VGS = 0V, f = 1.0MHz | 2 | ||
| Output Capacitance | Coss | 114 | pF | VDS = -25V, VGS = 0V, f = 1.0MHz | 2 | ||
| Reverse Transfer Capacitance | Crss | 92 | pF | VDS = -25V, VGS = 0V, f = 1.0MHz | 2 | ||
| Gate Resistance | RG | 3.3 | Ω | VDS = 0V, VGS = 0V, f = 1.0MHz | 2 | ||
| Total Gate Charge | QG | 6.8 | nC | VDS = -15V, VGS = -4.5V, ID = -6A | 2 | ||
| Total Gate Charge | QG | 13.7 | nC | VDS = -15V, VGS = -10V, ID = -6A | 2 | ||
| Gate-Source Charge | QGS | 1.6 | nC | VDS = -15V, VGS = -10V, ID = -6A | 2 | ||
| Gate-Drain Charge | QGD | 4.2 | nC | VDS = -15V, VGS = -10V, ID = -6A | 2 | ||
| Turn-On Delay Time | td(on) | 6.4 | ns | VDS = -15V, VGS = -10V, ID = -1A, RG = 6.0Ω | 2 | ||
| Rise Time | tr | 5.3 | ns | VDS = -15V, VGS = -10V, ID = -1A, RG = 6.0Ω | 2 | ||
| Turn-Off Delay Time | td(off) | 26.5 | ns | VDS = -15V, VGS = -10V, ID = -1A, RG = 6.0Ω | 2 | ||
| Fall Time | tf | 14.7 | ns | VDS = -15V, VGS = -10V, ID = -1A, RG = 6.0Ω | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | • Terminal Connections Indicator: See Diagram • Terminals: Finish - Matte Tin annealed over Copper lead | 1 |
CAD (KiCad official)
- Symbol:
DMP3056LSD - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
dmp3056lsd-etched.step/dmp3056lsd-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmp3056lsd.step/dmp3056lsd.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (5 pp, sha256
819eee2f89a46ae5, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DMP3056LSD
**Diodes Incorporated** · MOSFETs · SO-8
DMP3056LSD from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of P-channel MOSFET 1. |
| 2 | G1 | input | Gate of P-channel MOSFET 1, with VGSS rated ±20 V. |
| 3 | S2 | passive | Source of P-channel MOSFET 2. |
| 4 | G2 | input | Gate of P-channel MOSFET 2, with VGSS rated ±20 V. |
| 5 | D2 | passive | Drain of P-channel MOSFET 2, with VDSS rated -30 V. |
| 6 | D2 | passive | Drain of P-channel MOSFET 2, with VDSS rated -30 V, internally tied to pin 5. |
| 7 | D1 | passive | Drain of P-channel MOSFET 1, with VDSS rated -30 V. |
| 8 | D1 | passive | Drain of P-channel MOSFET 1, with VDSS rated -30 V, internally tied to pin 7. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -30 | | | V | VGS = 0V, ID = -250µA | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | -1 | µA | VDS = -30V, VGS = 0V | 2 |
| Gate-Source Leakage | IGSS | -100 | | 100 | nA | VGS = ±20V, VDS = 0V | 2 |
| Gate-Source Leakage | IGSS | -800 | | 800 | nA | VGS = ±25V, VDS = 0V | 2 |
| Gate Threshold Voltage | VGS(th) | -1 | -1.7 | -2.1 | V | VDS = VGS, ID = -250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | | 45 | mΩ | VGS = -10V, ID = -6.0A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | | 65 | mΩ | VGS = -4.5V, ID = -5.0A | 2 |
| Diode Forward Voltage | VSD | -0.5 | | -1.2 | V | VGS = 0V, IS = -1.7A | 2 |
| Drain-Source Voltage | VDSS | | | -30 | V | TA = +25°C | 2 |
| Gate-Source Voltage | VGSS | -20 | | 20 | V | TA = +25°C | 2 |
| Drain Current | ID | | | -6.9 | A | Steady state, TA = +25°C | 2 |
| Drain Current | ID | | | -5.8 | A | Steady state, TA = +70°C | 2 |
| Pulsed Drain Current | IDM | | | -24 | A | Pulse width ≤10μS, Duty Cycle ≤1% | 2 |
| Total Power Dissipation | PD | | | 2.5 | W | Device mounted on 2 oz. 1" x 1" Cu pads on 2" x 2" FR-4 PCB | 2 |
| Thermal Resistance, Junction to Ambient | RθJA | | | 50 | °C/W | Device mounted on 2 oz. 1" x 1" Cu pads on 2" x 2" FR-4 PCB | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 | | 150 | °C | | 2 |
| Forward Transconductance | gfs | | 8 | | S | VDS = -10V, ID = -5.3A | 2 |
| Input Capacitance | Ciss | | 722 | | pF | VDS = -25V, VGS = 0V, f = 1.0MHz | 2 |
| Output Capacitance | Coss | | 114 | | pF | VDS = -25V, VGS = 0V, f = 1.0MHz | 2 |
| Reverse Transfer Capacitance | Crss | | 92 | | pF | VDS = -25V, VGS = 0V, f = 1.0MHz | 2 |
| Gate Resistance | RG | | 3.3 | | Ω | VDS = 0V, VGS = 0V, f = 1.0MHz | 2 |
| Total Gate Charge | QG | | 6.8 | | nC | VDS = -15V, VGS = -4.5V, ID = -6A | 2 |
| Total Gate Charge | QG | | 13.7 | | nC | VDS = -15V, VGS = -10V, ID = -6A | 2 |
| Gate-Source Charge | QGS | | 1.6 | | nC | VDS = -15V, VGS = -10V, ID = -6A | 2 |
| Gate-Drain Charge | QGD | | 4.2 | | nC | VDS = -15V, VGS = -10V, ID = -6A | 2 |
| Turn-On Delay Time | td(on) | | 6.4 | | ns | VDS = -15V, VGS = -10V, ID = -1A, RG = 6.0Ω | 2 |
| Rise Time | tr | | 5.3 | | ns | VDS = -15V, VGS = -10V, ID = -1A, RG = 6.0Ω | 2 |
| Turn-Off Delay Time | td(off) | | 26.5 | | ns | VDS = -15V, VGS = -10V, ID = -1A, RG = 6.0Ω | 2 |
| Fall Time | tf | | 14.7 | | ns | VDS = -15V, VGS = -10V, ID = -1A, RG = 6.0Ω | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | • Terminal Connections Indicator: See Diagram • Terminals: Finish - Matte Tin annealed over Copper lead | 1 |
## CAD (KiCad official)
- Symbol: `DMP3056LSD`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `dmp3056lsd-etched.step` / `dmp3056lsd-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmp3056lsd.step` / `dmp3056lsd.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://www.diodes.com/assets/Datasheets/DMP3056LSD.pdf) (5 pp, sha256 `819eee2f89a46ae5`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dmp3056lsd-datasheet.pdf)