component
DMP3050LSS-13
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Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DMP3050LSS-13
Diodes Incorporated · MOSFETs · SO-8
DMP3050LSS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied internally to pins 2 and 3. |
| 2 | S | passive | Source of the P-channel MOSFET, tied internally to pins 1 and 3. |
| 3 | S | passive | Source of the P-channel MOSFET, tied internally to pins 1 and 2. |
| 4 | G | input | Gate of the P-channel MOSFET, with a gate-source voltage rating of ±25V and a threshold of -1.0V to -2.0V. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied internally to pins 6, 7 and 8, rated for -30V drain-source voltage. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied internally to pins 5, 7 and 8, rated for -30V drain-source voltage. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied internally to pins 5, 6 and 8, rated for -30V drain-source voltage. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied internally to pins 5, 6 and 7, rated for -30V drain-source voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | • Terminal Connections Indicator: See diagram • Terminals: Finish ⎯ Matte Tin annealed over Copper leadframe. | 1 |
CAD (KiCad official)
- Symbol:
DMP3050LSS-13 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
dmp3050lss-13-etched.step/dmp3050lss-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmp3050lss-13.step/dmp3050lss-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (6 pp, sha256
05d1e23dc59915c8, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DMP3050LSS-13
**Diodes Incorporated** · MOSFETs · SO-8
DMP3050LSS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied internally to pins 2 and 3. |
| 2 | S | passive | Source of the P-channel MOSFET, tied internally to pins 1 and 3. |
| 3 | S | passive | Source of the P-channel MOSFET, tied internally to pins 1 and 2. |
| 4 | G | input | Gate of the P-channel MOSFET, with a gate-source voltage rating of ±25V and a threshold of -1.0V to -2.0V. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied internally to pins 6, 7 and 8, rated for -30V drain-source voltage. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied internally to pins 5, 7 and 8, rated for -30V drain-source voltage. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied internally to pins 5, 6 and 8, rated for -30V drain-source voltage. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied internally to pins 5, 6 and 7, rated for -30V drain-source voltage. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | • Terminal Connections Indicator: See diagram • Terminals: Finish ⎯ Matte Tin annealed over Copper leadframe. | 1 |
## CAD (KiCad official)
- Symbol: `DMP3050LSS-13`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `dmp3050lss-13-etched.step` / `dmp3050lss-13-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmp3050lss-13.step` / `dmp3050lss-13.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://www.diodes.com/assets/Datasheets/DMP3050LSS-13.pdf) (6 pp, sha256 `05d1e23dc59915c8`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dmp3050lss-13-datasheet.pdf)