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DMP2200UDW-7
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Diodes Incorporated MOSFETs, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DMP2200UDW-7
Diodes Incorporated · MOSFETs · SOT-363
DMP2200UDW-7 from Diodes Incorporated, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source terminal of Q1, one of the two P-channel enhancement MOSFETs; the device drain-source voltage rating is -20 V. |
| 2 | G1 | input | Gate of Q1 with an integrated gate protection diode (ESD protected); the gate-source voltage limit is ±8 V. |
| 3 | D2 | passive | Drain terminal of Q2, one of the two P-channel MOSFETs; continuous drain current is -0.9 A at TA = +25°C. |
| 4 | S2 | passive | Source terminal of Q2, one of the two P-channel MOSFETs; the device drain-source voltage rating is -20 V. |
| 5 | G2 | input | Gate of Q2 with an integrated gate protection diode (ESD protected); the gate-source voltage limit is ±8 V. |
| 6 | D1 | passive | Drain terminal of Q1, one of the two P-channel MOSFETs; continuous drain current is -0.9 A at TA = +25°C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -20 | V | VGS = 0V, ID = 250µA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -1 | µA | VDS = -16V, VGS = 0V | 2 | ||
| Gate-Body Leakage | IGSS | -10 | 10 | µA | VGS = ±8V, VDS = 0V | 2 | |
| Gate Threshold Voltage | VGS(th) | -0.4 | -1.2 | V | VDS = VGS, ID = -250µA | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 180 | 260 | mΩ | VGS = -4.5V, ID = -0.88A | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 240 | 500 | mΩ | VGS = -2.5V, ID = -0.71A | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 320 | 1000 | mΩ | VGS = -1.8V, ID = -0.20A | 2 | |
| Diode Forward Voltage | VSD | -0.8 | -1.2 | V | VGS = 0V, IS = -0.48A | 2 | |
| Drain-Source Voltage | VDSS | -20 | V | TA = +25°C (Maximum Ratings) | 2 | ||
| Gate-Source Voltage | VGSS | -8 | 8 | V | Maximum Ratings | 2 | |
| Continuous Drain Current | ID | -0.9 | A | TA = +25°C (Note 6) | 2 | ||
| Continuous Drain Current | ID | -0.7 | A | TA = +85°C (Note 6) | 2 | ||
| Total Power Dissipation | PD | 0.45 | W | Note 5 (FR-4, minimum recommended pad layout) | 2 | ||
| Total Power Dissipation | PD | 0.6 | W | Note 6 (FR-4, 1 inch square copper plate) | 2 | ||
| Thermal Resistance, Junction to Ambient, Steady State | RθJA | 275 | °C/W | Note 5 (minimum recommended pad layout) | 2 | ||
| Thermal Resistance, Junction to Ambient, Steady State | RθJA | 208 | °C/W | Note 6 (1 inch square copper plate) | 2 | ||
| Thermal Resistance, Junction to Case | RθJC | 72 | °C/W | 2 | |||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 | ||
| Thermal Resistance, Junction to Ambient (transient thermal note) | RθJA | 271 | °C/W | Figure 13 note: R(t) = r(t) * RθJA | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | • Terminals Connections: See Diagram • Terminals: Finish - Matte Tin Annealed over Alloy 42 Leadframe. | 1 |
CAD (KiCad official)
- Symbol:
DMP2200UDW-7 - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files:
dmp2200udw-7-etched.step/dmp2200udw-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmp2200udw-7.step/dmp2200udw-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (6 pp, sha256
76e2ed080efb1598, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DMP2200UDW-7
**Diodes Incorporated** · MOSFETs · SOT-363
DMP2200UDW-7 from Diodes Incorporated, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source terminal of Q1, one of the two P-channel enhancement MOSFETs; the device drain-source voltage rating is -20 V. |
| 2 | G1 | input | Gate of Q1 with an integrated gate protection diode (ESD protected); the gate-source voltage limit is ±8 V. |
| 3 | D2 | passive | Drain terminal of Q2, one of the two P-channel MOSFETs; continuous drain current is -0.9 A at TA = +25°C. |
| 4 | S2 | passive | Source terminal of Q2, one of the two P-channel MOSFETs; the device drain-source voltage rating is -20 V. |
| 5 | G2 | input | Gate of Q2 with an integrated gate protection diode (ESD protected); the gate-source voltage limit is ±8 V. |
| 6 | D1 | passive | Drain terminal of Q1, one of the two P-channel MOSFETs; continuous drain current is -0.9 A at TA = +25°C. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -20 | | | V | VGS = 0V, ID = 250µA | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | -1 | µA | VDS = -16V, VGS = 0V | 2 |
| Gate-Body Leakage | IGSS | -10 | | 10 | µA | VGS = ±8V, VDS = 0V | 2 |
| Gate Threshold Voltage | VGS(th) | -0.4 | | -1.2 | V | VDS = VGS, ID = -250µA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 180 | 260 | mΩ | VGS = -4.5V, ID = -0.88A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 240 | 500 | mΩ | VGS = -2.5V, ID = -0.71A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 320 | 1000 | mΩ | VGS = -1.8V, ID = -0.20A | 2 |
| Diode Forward Voltage | VSD | | -0.8 | -1.2 | V | VGS = 0V, IS = -0.48A | 2 |
| Drain-Source Voltage | VDSS | | | -20 | V | TA = +25°C (Maximum Ratings) | 2 |
| Gate-Source Voltage | VGSS | -8 | | 8 | V | Maximum Ratings | 2 |
| Continuous Drain Current | ID | | | -0.9 | A | TA = +25°C (Note 6) | 2 |
| Continuous Drain Current | ID | | | -0.7 | A | TA = +85°C (Note 6) | 2 |
| Total Power Dissipation | PD | | | 0.45 | W | Note 5 (FR-4, minimum recommended pad layout) | 2 |
| Total Power Dissipation | PD | | | 0.6 | W | Note 6 (FR-4, 1 inch square copper plate) | 2 |
| Thermal Resistance, Junction to Ambient, Steady State | RθJA | | | 275 | °C/W | Note 5 (minimum recommended pad layout) | 2 |
| Thermal Resistance, Junction to Ambient, Steady State | RθJA | | | 208 | °C/W | Note 6 (1 inch square copper plate) | 2 |
| Thermal Resistance, Junction to Case | RθJC | | | 72 | °C/W | | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 | | 150 | °C | | 2 |
| Thermal Resistance, Junction to Ambient (transient thermal note) | RθJA | | 271 | | °C/W | Figure 13 note: R(t) = r(t) * RθJA | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | • Terminals Connections: See Diagram • Terminals: Finish - Matte Tin Annealed over Alloy 42 Leadframe. | 1 |
## CAD (KiCad official)
- Symbol: `DMP2200UDW-7`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files: `dmp2200udw-7-etched.step` / `dmp2200udw-7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmp2200udw-7.step` / `dmp2200udw-7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588936998224056320) (6 pp, sha256 `76e2ed080efb1598`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dmp2200udw-7-datasheet.pdf)