component
DMP2066LSS-13
Public Made by Adomby adom
Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownDMP2066LSS-13
Diodes Incorporated · MOSFETs · SO-8
DMP2066LSS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied to pins 2 and 3. |
| 2 | S | passive | Source of the P-channel MOSFET, tied to pins 1 and 3. |
| 3 | S | passive | Source of the P-channel MOSFET, tied to pins 1 and 2. |
| 4 | G | input | Gate of the P-channel MOSFET, with a threshold VGS(TH) of -0.6V to -1.2V and a maximum VGSS of ±12V. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied to pins 6, 7 and 8, with VDSS of -20V and continuous ID of -6.5A at TA=+25°C. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied to pins 5, 7 and 8, with VDSS of -20V. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied to pins 5, 6 and 8, with VDSS of -20V. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied to pins 5, 6 and 7, with VDSS of -20V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -20 | V | VGS = 0V, ID = -250μA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -1 | μA | VDS = -20V, VGS = 0V | 2 | ||
| Gate-Source Leakage | IGSS | 100 | nA | VGS = 12V, VDS = 0V | 2 | ||
| Gate Threshold Voltage | VGS(TH) | -0.6 | -1.2 | V | VDS = VGS, ID = -250μA | 2 | |
| Static Drain-Source On-Resistance (VGS = -4.5V) | RDS(ON) | 40 | mΩ | VGS = -4.5V, ID = -5.8A | 2 | ||
| Static Drain-Source On-Resistance (VGS = -2.5V) | RDS(ON) | 70 | mΩ | VGS = -2.5V, ID = -3.8A | 2 | ||
| Diode Forward Voltage | VSD | -0.5 | -0.72 | -1.4 | V | VGS = 0V, IS = -2.1A | 2 |
| Drain-Source Voltage | VDSS | -20 | V | 2 | |||
| Gate-Source Voltage | VGSS | 12 | V | 2 | |||
| Drain Current (steady state) | ID | -6.5 | A | Steady state, TA = +25°C (Note 5) | 2 | ||
| Drain Current (steady state) | ID | -5.2 | A | Steady state, TA = +70°C (Note 5) | 2 | ||
| Pulsed Drain Current | IDM | -26 | A | 10μs Pulse, Duty Cycle = 1% | 2 | ||
| Total Power Dissipation | PD | 2.5 | W | Note 5: device mounted on FR-4 substrate PC board, 2oz copper, with 1inch square copper plate | 2 | ||
| Thermal Resistance, Junction to Ambient | RJA | 50 | °C/W | Note 5: device mounted on FR-4 substrate PC board, 2oz copper, with 1inch square copper plate | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | Terminals Connections: See Diagram Terminals: Finish - Matte Tin Annealed over Copper Lead | 1 |
CAD (land: KiCad; 3D: generated from the datasheet)
- Symbol:
DMP2066LSS-13 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8, generated on the KiCad land (body 3.85 x 4.9 mm, terminals on the pads, 1.45 mm tall, datasheet A, nominal). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
- 3D model files:
dmp2066lss-13-etched.step/dmp2066lss-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmp2066lss-13.step/dmp2066lss-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (6 pp, sha256
6f5e89de4446fe0f, retrieved 2026-11-13, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).