component
DMP2038USS-13
Public Made by Adomby adom
Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DMP2038USS-13
Diodes Incorporated · MOSFETs · SO-8
DMP2038USS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, shown on the top-view pin-out with pins 2 and 3. |
| 2 | S | passive | Source of the P-channel MOSFET, shown on the top-view pin-out with pins 1 and 3. |
| 3 | S | passive | Source of the P-channel MOSFET, shown on the top-view pin-out with pins 1 and 2. |
| 4 | G | input | Gate of the P-channel MOSFET; VGSS is rated at 8V and the gate threshold VGS(TH) is -0.4V to -1.1V at ID = -250µA. |
| 5 | D | passive | Drain of the P-channel MOSFET, shown on the top-view pin-out with pins 6, 7 and 8; VDSS is -20V. |
| 6 | D | passive | Drain of the P-channel MOSFET, shown on the top-view pin-out with pins 5, 7 and 8; VDSS is -20V. |
| 7 | D | passive | Drain of the P-channel MOSFET, shown on the top-view pin-out with pins 5, 6 and 8; VDSS is -20V. |
| 8 | D | passive | Drain of the P-channel MOSFET, shown on the top-view pin-out with pins 5, 6 and 7; VDSS is -20V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -20 | V | VGS = 0V, ID = -250µA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -1 | µA | VDS = -16V, VGS = 0V | 2 | ||
| Gate-Source Leakage | IGSS | 100 | nA | VGS = 8V, VDS = 0V | 2 | ||
| Gate Threshold Voltage | VGS(TH) | -0.4 | -1.1 | V | VDS = VGS, ID = -250µA | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 24 | 38 | mΩ | VGS = -4.5V, ID = -5A | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 33 | 56 | mΩ | VGS = -2.5V, ID = -4.3A | 2 | |
| Diode Forward Voltage | VSD | -0.7 | -1.2 | V | VGS = 0V, IS = -2.1A | 2 | |
| Drain-Source Voltage | VDSS | -20 | V | 2 | |||
| Gate-Source Voltage | VGSS | 8 | V | 2 | |||
| Drain Current, steady state | ID | -6.5 | A | Steady state, TA = +25°C | 2 | ||
| Drain Current, steady state | ID | -5.2 | A | Steady state, TA = +70°C | 2 | ||
| Pulsed Drain Current | IDM | -25 | A | 10µs pulse, duty cycle = 1% | 2 | ||
| Maximum Continuous Body Diode Forward Current | IS | 2 | A | Note 6 | 2 | ||
| Avalanche Current | IAS | 13.2 | A | L = 0.3mH (Note 7) | 2 | ||
| Avalanche Energy | EAS | 26 | mJ | L = 0.3mH (Note 7) | 2 | ||
| Total Power Dissipation | PD | 2.5 | W | Note 6 | 2 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 50 | °C/W | Note 6 | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | Terminals Connections: See Diagram Terminals: Finish - Matte Tin Annealed over Copper Lead | 1 |
CAD (KiCad official)
- Symbol:
DMP2038USS-13 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
dmp2038uss-13-etched.step/dmp2038uss-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmp2038uss-13.step/dmp2038uss-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (6 pp, sha256
727a30174d3279f8, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DMP2038USS-13
**Diodes Incorporated** · MOSFETs · SO-8
DMP2038USS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, shown on the top-view pin-out with pins 2 and 3. |
| 2 | S | passive | Source of the P-channel MOSFET, shown on the top-view pin-out with pins 1 and 3. |
| 3 | S | passive | Source of the P-channel MOSFET, shown on the top-view pin-out with pins 1 and 2. |
| 4 | G | input | Gate of the P-channel MOSFET; VGSS is rated at 8V and the gate threshold VGS(TH) is -0.4V to -1.1V at ID = -250µA. |
| 5 | D | passive | Drain of the P-channel MOSFET, shown on the top-view pin-out with pins 6, 7 and 8; VDSS is -20V. |
| 6 | D | passive | Drain of the P-channel MOSFET, shown on the top-view pin-out with pins 5, 7 and 8; VDSS is -20V. |
| 7 | D | passive | Drain of the P-channel MOSFET, shown on the top-view pin-out with pins 5, 6 and 8; VDSS is -20V. |
| 8 | D | passive | Drain of the P-channel MOSFET, shown on the top-view pin-out with pins 5, 6 and 7; VDSS is -20V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -20 | | | V | VGS = 0V, ID = -250µA | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | -1 | µA | VDS = -16V, VGS = 0V | 2 |
| Gate-Source Leakage | IGSS | | | 100 | nA | VGS = 8V, VDS = 0V | 2 |
| Gate Threshold Voltage | VGS(TH) | -0.4 | | -1.1 | V | VDS = VGS, ID = -250µA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 24 | 38 | mΩ | VGS = -4.5V, ID = -5A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 33 | 56 | mΩ | VGS = -2.5V, ID = -4.3A | 2 |
| Diode Forward Voltage | VSD | | -0.7 | -1.2 | V | VGS = 0V, IS = -2.1A | 2 |
| Drain-Source Voltage | VDSS | | | -20 | V | | 2 |
| Gate-Source Voltage | VGSS | | | 8 | V | | 2 |
| Drain Current, steady state | ID | | | -6.5 | A | Steady state, TA = +25°C | 2 |
| Drain Current, steady state | ID | | | -5.2 | A | Steady state, TA = +70°C | 2 |
| Pulsed Drain Current | IDM | | | -25 | A | 10µs pulse, duty cycle = 1% | 2 |
| Maximum Continuous Body Diode Forward Current | IS | | | 2 | A | Note 6 | 2 |
| Avalanche Current | IAS | | | 13.2 | A | L = 0.3mH (Note 7) | 2 |
| Avalanche Energy | EAS | | | 26 | mJ | L = 0.3mH (Note 7) | 2 |
| Total Power Dissipation | PD | | | 2.5 | W | Note 6 | 2 |
| Thermal Resistance, Junction to Ambient | RθJA | | | 50 | °C/W | Note 6 | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 | | 150 | °C | | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | Terminals Connections: See Diagram Terminals: Finish - Matte Tin Annealed over Copper Lead | 1 |
## CAD (KiCad official)
- Symbol: `DMP2038USS-13`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `dmp2038uss-13-etched.step` / `dmp2038uss-13-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmp2038uss-13.step` / `dmp2038uss-13.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885249380401152) (6 pp, sha256 `727a30174d3279f8`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dmp2038uss-13-datasheet.pdf)