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DMN61D8LQ-7

Public Made by Adom

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Diodes Incorporated MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DMN61D8LQ-7

Diodes Incorporated · MOSFETs · SOT-23

DMN61D8LQ-7 from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate input Logic-level gate input with internal 10k series resistor and 100k pulldown, ESD protected, rated VGSS ±12V with RDS(ON) max 1.8Ω at VGS=5V and 2.4Ω at VGS=3V.
2 Source passive MOSFET source terminal, normally tied to ground, with continuous body diode forward current rating of 0.5A.
3 Drain passive Drain output connecting to the relay or inductive load, rated 60V VDSS and 470mA continuous at TA=+25°C with internal active clamp.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-23
Category Triode/MOS Tube/Transistor
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDSS 60 V TA = +25°C 2
Gate-Source Voltage VGSS -12 12 V TA = +25°C 2
Continuous Drain Current ID 470 mA Steady state, TA = +25°C (Note 7) 2
Continuous Drain Current ID 370 mA Steady state, TA = +70°C (Note 7) 2
Maximum Continuous Body Diode Forward Current IS 0.5 A Note 6 2
Single Pulse Drain-to-Source Avalanche Energy EZ 200 mJ Inductive loads of 80Ω or higher, TJ initial = +85°C 2
Peak Power Dissipation, Drain-to-Source PPK 20 W Non repetitive current square pulse 1.0ms, TJ initial = +85°C 2
Load Dump Pulse, Drain-to-Source ELD1 60 V RSOURCE = 0.5Ω, t = 300ms, loads of 80Ω or higher, TJ initial = +85°C 2
Inductive Switching Transient 1 ELD2 100 V RSOURCE = 10Ω, t = 2.0ms, loads of 80Ω or higher, TJ initial = +85°C 2
Inductive Switching Transient 2 ELD3 300 V RSOURCE = 4.0Ω, t = 50µs, loads of 80Ω or higher, TJ initial = +85°C 2
Reverse Battery, 10 Minutes Rev-Bat -14 V Drain-to-Source, loads of 80Ω or more 2
Dual Voltage Jump Start, 10 Minutes Dual-Volt 28 V Drain-to-Source 2
ESD Human Body Model ESD 4000 V HBM 2
Total Power Dissipation PD 390 mW Note 6, minimum recommended pad layout 2
Thermal Resistance, Junction to Ambient RθJA 321 °C/W Steady state, Note 6 2
Total Power Dissipation PD 610 mW Note 7, 1"x1" FR-4 2oz copper 2
Thermal Resistance, Junction to Ambient RθJA 208 °C/W Steady state, Note 7 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2
Drain-Source Breakdown Voltage BVDSS 60 V VGS = 0V, ID = 10mA 3
Zero Gate Voltage Drain Current IDSS 50 µA VDS = 60V, VGS = 0V 3
Zero Gate Voltage Drain Current IDSS 0.5 µA VDS = 12V, VGS = 0V 3
Gate-Source Leakage IGSS -90 90 µA VGS = ±5V, VDS = 0V 3
Gate-Source Leakage IGSS -60 60 µA VGS = ±3V, VDS = 0V 3
Gate Threshold Voltage VGS(TH) 1.3 2 V VDS = VGS, ID = 1mA 3
Static Drain-Source On-Resistance RDS(ON) 1.1 1.8 Ω VGS =5V, ID = 0.15A 3
Static Drain-Source On-Resistance RDS(ON) 1.4 2.4 Ω VGS = 3V, ID = 0.15A 3
Forward Transfer Admittance /Yfs/ 80 ms VDS =12V, ID = 0.15A 3
Diode Forward Voltage VSD 1.2 V VGS = 0V, IS = 0.15A 3
Input Capacitance Ciss 12.9 pF VDS = 12V, VGS = 0V, f = 1.0MHz 3
Output Capacitance Coss 17 pF VDS = 12V, VGS = 0V, f = 1.0MHz 3
Reverse Transfer Capacitance Crss 0.84 pF VDS = 12V, VGS = 0V, f = 1.0MHz 3
Total Gate Charge Qg 0.74 nC VGS = 5V, VDS = 12V, ID =150mA 3
Gate-Source Charge Qgs 0.19 nC VGS = 5V, VDS = 12V, ID =150mA 3
Gate-Drain Charge Qgd 0.16 nC VGS = 5V, VDS = 12V, ID =150mA 3
Turn-On Delay Time tD(ON) 131 ns VDD = 12V, VGS = 5V 3
Turn-On Rise Time tR 301 ns VDD = 12V, VGS = 5V 3
Turn-Off Delay Time tD(OFF) 582 ns VDD = 12V, VGS = 5V 3
Turn-Off Fall Time tF 440 ns VDD = 12V, VGS = 5V 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin  Terminals: Matte Tin Finish Annealed over Alloy 42 Leadframe (Lead-Free Plating). Solderable per MIL-STD-202, Method 208 1

CAD (KiCad official)

  • Symbol: DMN61D8LQ-7
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: dmn61d8lq-7-etched.step / dmn61d8lq-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dmn61d8lq-7.step / dmn61d8lq-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (7 pp, sha256 81b3589d9a313eab, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF