# DMN6070SSD-13

**Diodes Incorporated** · MOSFETs · SO-8

DMN6070SSD-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of N-channel MOSFET 1; the device is rated for 60V drain-source (VDSS) with ±20V gate-source (VGSS). |
| 2 | G1 | input | Gate of N-channel MOSFET 1; gate-source voltage is rated ±20V (VGSS). |
| 3 | S2 | passive | Source of N-channel MOSFET 2; the device is rated for 60V drain-source (VDSS) with ±20V gate-source (VGSS). |
| 4 | G2 | input | Gate of N-channel MOSFET 2; gate-source voltage is rated ±20V (VGSS). |
| 5 | D2 | passive | Drain of N-channel MOSFET 2; the device is rated for 60V drain-source (VDSS) and 4.1A continuous drain current at TA = +25°C (t<10s). |
| 6 | D2 | passive | Drain of N-channel MOSFET 2; the device is rated for 60V drain-source (VDSS) and 4.1A continuous drain current at TA = +25°C (t<10s). |
| 7 | D1 | passive | Drain of N-channel MOSFET 1; the device is rated for 60V drain-source (VDSS) and 4.1A continuous drain current at TA = +25°C (t<10s). |
| 8 | D1 | passive | Drain of N-channel MOSFET 1; the device is rated for 60V drain-source (VDSS) and 4.1A continuous drain current at TA = +25°C (t<10s). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | 60 |  |  | V | ID = 250μA, VGS = 0V | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 1 | μA | VDS = 60V, VGS = 0V | 2 |
| Gate-Source Leakage | IGSS | -100 |  | 100 | nA | VGS = ±16V, VDS = 0V | 2 |
| Gate Threshold Voltage | VGS(th) | 1 |  | 3 | V | ID = 250μA, VDS = VGS | 2 |
| Static Drain-Source On-Resistance | RDS(ON) |  | 68 | 80 | mΩ | VGS = 10V, ID = 4.5A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) |  | 70 | 100 | mΩ | VGS = 4.5V, ID = 3.5A | 2 |
| Diode Forward Voltage | VSD |  | 0.75 | 1.1 | V | IS = 12A, VGS = 0V | 2 |
| Drain-Source Voltage | VDSS |  |  | 60 | V |  | 2 |
| Gate-Source Voltage | VGSS | -20 |  | 20 | V |  | 2 |
| Continuous Drain Current | ID |  |  | 3.3 | A | VGS = 10V, steady state, TA = +25°C | 2 |
| Continuous Drain Current | ID |  |  | 2.6 | A | VGS = 10V, steady state, TA = +70°C | 2 |
| Continuous Drain Current | ID |  |  | 4.1 | A | VGS = 10V, t<10s, TA = +25°C | 2 |
| Continuous Drain Current | ID |  |  | 3.4 | A | VGS = 10V, t<10s, TA = +70°C | 2 |
| Maximum Continuous Body Diode Forward Current | IS |  |  | 2 | A |  | 2 |
| Pulsed Drain Current | IDM |  |  | 12 | A | 10μs pulse, duty cycle = 1% | 2 |
| Avalanche Current | IAS |  |  | 10 | A | L = 0.1mH | 2 |
| Avalanche Energy | EAS |  |  | 5.9 | mJ | L = 0.1mH | 2 |
| Total Power Dissipation | PD |  |  | 1.2 | W | Note 5: FR-4 PCB, 2oz copper, minimum recommended pad layout | 2 |
| Total Power Dissipation | PD |  |  | 1.5 | W | Note 6: FR-4 PCB, 2oz copper, 1 inch square copper plate | 2 |
| Thermal Resistance, Junction to Ambient, steady state | RθJA |  |  | 104 | °C/W | Note 5, steady state | 2 |
| Thermal Resistance, Junction to Ambient, t<10s | RθJA |  |  | 61 | °C/W | Note 5, t<10s | 2 |
| Thermal Resistance, Junction to Ambient, steady state | RθJA |  |  | 83 | °C/W | Note 6, steady state | 2 |
| Thermal Resistance, Junction to Ambient, t<10s | RθJA |  |  | 50 | °C/W | Note 6, t<10s | 2 |
| Thermal Resistance, Junction to Case | RθJC |  |  | 14.5 | °C/W |  | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 150 | °C |  | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC |  | Body Diode Reverse Recovery Charge Qrr, 12, nC IS = 12A, dI/dt = 100A/μs Notes: 5. Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. | 2 |
| contacts | Copper | tin | • Terminal Connections Indicator: See Diagram • Terminals: Finish ⎯ Matte Tin Annealed over Copper Leadframe | 1 |

## CAD (KiCad official)

- Symbol: `DMN6070SSD-13`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `dmn6070ssd-13-etched.step` / `dmn6070ssd-13-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmn6070ssd-13.step` / `dmn6070ssd-13.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885240119377920) (6 pp, sha256 `edf588e8a6a12bec`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dmn6070ssd-13-datasheet.pdf)