# DMN6040SSDQ-13

**Diodes Incorporated** · MOSFETs · SO-8

DMN6040SSDQ-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source terminal of MOSFET 1 (N-channel); the datasheet rates the device at VDSS 60 V and VGSS ±20 V. |
| 2 | G1 | input | Gate terminal of MOSFET 1; gate-source voltage is rated at ±20 V (VGSS). |
| 3 | S2 | passive | Source terminal of MOSFET 2 (N-channel); the datasheet rates the device at VDSS 60 V and VGSS ±20 V. |
| 4 | G2 | input | Gate terminal of MOSFET 2; gate-source voltage is rated at ±20 V (VGSS). |
| 5 | D2 | passive | Drain terminal of MOSFET 2 (N-channel); drain-source voltage is rated at 60 V (VDSS). |
| 6 | D2 | passive | Drain terminal of MOSFET 2 (N-channel); drain-source voltage is rated at 60 V (VDSS). |
| 7 | D1 | passive | Drain terminal of MOSFET 1 (N-channel); drain-source voltage is rated at 60 V (VDSS). |
| 8 | D1 | passive | Drain terminal of MOSFET 1 (N-channel); drain-source voltage is rated at 60 V (VDSS). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS |  |  | 60 | V |  | 2 |
| Gate-Source Voltage | VGSS | -20 |  | 20 | V |  | 2 |
| Continuous Drain Current, steady state | ID |  |  | 5 | A | VGS = 10V, TA = +25°C, steady state | 2 |
| Continuous Drain Current, steady state | ID |  |  | 4.1 | A | VGS = 10V, TA = +70°C, steady state | 2 |
| Continuous Drain Current, t<10s | ID |  |  | 6.6 | A | VGS = 10V, TA = +25°C, t<10s | 2 |
| Continuous Drain Current, t<10s | ID |  |  | 5.3 | A | VGS = 10V, TA = +70°C, t<10s | 2 |
| Maximum Body Diode Forward Current | IS |  |  | 2.5 | A |  | 2 |
| Pulsed Drain Current | IDM |  |  | 30 | A | 10µs pulse, duty cycle = 1% | 2 |
| Pulsed Body Diode Forward Current | ISM |  |  | 30 | A | 10µs pulse, duty cycle = 1% | 2 |
| Avalanche Current | IAS |  |  | 14.2 | A | L = 0.1mH | 2 |
| Avalanche Energy | EAS |  |  | 10 | mJ | L = 0.1mH | 2 |
| Total Power Dissipation (Note 6) | PD |  |  | 1.3 | W | TA = +25°C | 2 |
| Total Power Dissipation (Note 6) | PD |  |  | 0.8 | W | TA = +70°C | 2 |
| Total Power Dissipation (Note 7) | PD |  |  | 1.7 | W | TA = +25°C | 2 |
| Total Power Dissipation (Note 7) | PD |  |  | 1.1 | W | TA = +70°C | 2 |
| Thermal Resistance, Junction to Ambient (Note 6), steady state | RθJA |  |  | 102 | °C/W | Steady state | 2 |
| Thermal Resistance, Junction to Ambient (Note 6), t<10s | RθJA |  |  | 61 | °C/W | t<10s | 2 |
| Thermal Resistance, Junction to Ambient (Note 7), steady state | RθJA |  |  | 75 | °C/W | Steady state | 2 |
| Thermal Resistance, Junction to Ambient (Note 7), t<10s | RθJA |  |  | 50 | °C/W | t<10s | 2 |
| Thermal Resistance, Junction to Case (Note 7) | RθJC |  |  | 14.5 | °C/W |  | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 150 | °C |  | 2 |
| Drain-Source Breakdown Voltage | BVDSS | 60 |  |  | V | VGS = 0V, ID = 250µA | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 100 | nA | VDS = 60V, VGS = 0V | 2 |
| Gate-Source Leakage | IGSS |  |  | 100 | nA | VGS = ±20V, VDS = 0V | 2 |
| Gate Threshold Voltage | VGS(TH) | 1 |  | 3 | V | VDS = VGS, ID = 250µA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) |  | 30 | 40 | mΩ | VGS = 10V, ID = 4.5A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) |  | 35 | 55 | mΩ | VGS = 4.5V, ID = 3.5A | 2 |
| Diode Forward Voltage | VSD |  | 0.7 | 1.2 | V | VGS = 0V, IS = 1A | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC |  | Body Diode Reverse Recovery Charge QRR  11.9  nC IS = 4.3A, di/dt = 100A/µs Notes: 6. Device mounted on FR-4 PC board, with minimum recommended pad layout, single sided. | 2 |
| contacts | Copper | tin |  Terminal Connections: See Diagram  Terminals: Finish, Tin Finish Annealed over Copper Leadframe. | 1 |

## CAD (KiCad official)

- Symbol: `DMN6040SSDQ-13`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `dmn6040ssdq-13-etched.step` / `dmn6040ssdq-13-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmn6040ssdq-13.step` / `dmn6040ssdq-13.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885240115048448) (7 pp, sha256 `d555ce1af67abcd8`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dmn6040ssdq-13-datasheet.pdf)