Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

DMN53D0LDW-7

Diodes Incorporated · MOSFETs · SOT-363

DMN53D0LDW-7 from Diodes Incorporated, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S2 passive Source of MOSFET 2 (N-channel), bottom-left terminal in the top-view schematic.
2 G2 input Gate of MOSFET 2, ESD protected to 2kV with VGSS max ±20V and threshold 0.8V to 1.5V at 250µA.
3 D1 passive Drain of MOSFET 1, rated VDSS 50V and ID 360mA.
4 S1 passive Source of MOSFET 1 (N-channel), top-right terminal in the top-view schematic.
5 G1 input Gate of MOSFET 1, ESD protected to 2kV with VGSS max ±20V and threshold 0.8V to 1.5V at 250µA.
6 D2 passive Drain of MOSFET 2, rated VDSS 50V and ID 360mA.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-363
Category Transistors
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage BVDSS 50 V VGS = 0V, ID = 250µA 2
Zero Gate Voltage Drain Current IDSS 1 µA VDS = 50V, VGS = 0V 2
Gate-Body Leakage IGSS 10 µA VGS = ±20V, VDS = 0V 2
Gate Threshold Voltage VGS(TH) 0.8 1.5 V VDS = VGS, ID = 250µA 2
Static Drain-Source On-Resistance RDS(ON) 1 1.6 Ω VGS = 10V, ID = 500mA 2
Static Drain-Source On-Resistance RDS(ON) 1 2.5 Ω VGS = 4.5V, ID = 200mA 2
Static Drain-Source On-Resistance RDS(ON) 1.4 4.5 Ω VGS = 2.5V, ID = 100mA 2
Source-Drain Diode Forward Voltage VSD 0.8 1.4 V VGS = 0V, IS = 500mA 2
Drain Source Voltage VDSS 50 V TA = +25°C 2
Gate-Source Voltage VGSS 20 V TA = +25°C 2
Drain Current ID 360 mA TA = +25°C, Note 5 2
Total Power Dissipation PD 310 mW TA = +25°C, Note 5 2
Thermal Resistance, Junction to Ambient RθJA 411 °C/W TA = +25°C, Note 5 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2
Input Capacitance Ciss 46 pF VDS = 25V, VGS = 0V, f = 1.0MHz 2
Output Capacitance Coss 5.3 pF VDS = 25V, VGS = 0V, f = 1.0MHz 2
Reverse Transfer Capacitance Crss 4 pF VDS = 25V, VGS = 0V, f = 1.0MHz 2
Total Gate Charge Qg 0.6 nC VGS = 4.5V, VDS = 10V, ID = 250mA 2
Gate-Source Charge Qgs 0.2 nC VGS = 4.5V, VDS = 10V, ID = 250mA 2
Gate-Drain Charge Qgd 0.1 nC VGS = 4.5V, VDS = 10V, ID = 250mA 2
Turn-On Delay Time tD(ON) 2.7 ns VDD = 30V, VGS = 10V, RG = 25Ω, ID = 200mA 2
Turn-On Rise Time tR 2.5 ns VDD = 30V, VGS = 10V, RG = 25Ω, ID = 200mA 2
Turn-Off Delay Time tD(OFF) 19 ns VDD = 30V, VGS = 10V, RG = 25Ω, ID = 200mA 2
Turn-Off Fall Time tF 11 ns VDD = 30V, VGS = 10V, RG = 25Ω, ID = 200mA 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin  Terminals: Matte Tin Finish Annealed over Alloy 42 Leadframe (Lead Free Plating). Solderable per MIL-STD-202, Method 208 1

CAD (KiCad official)

  • Symbol: DMN53D0LDW-7
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SOT-363 (KiCad packages3D, STEP)
  • 3D model files: dmn53d0ldw-7-etched.step / dmn53d0ldw-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dmn53d0ldw-7.step / dmn53d0ldw-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (6 pp, sha256 fce8566506ad52be, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF