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DMN4800LSSL-13

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Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DMN4800LSSL-13

Diodes Incorporated · MOSFETs · SO-8

DMN4800LSSL-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source of the N-channel MOSFET, tied internally with pins 2 and 3.
2 S passive Source of the N-channel MOSFET, tied internally with pins 1 and 3.
3 S passive Source of the N-channel MOSFET, tied internally with pins 1 and 2.
4 G input Gate of the N-channel MOSFET, with a gate-source voltage rating of ±20 V.
5 D passive Drain of the N-channel MOSFET, tied internally with pins 6, 7 and 8; 30 V drain-source rating.
6 D passive Drain of the N-channel MOSFET, tied internally with pins 5, 7 and 8; 30 V drain-source rating.
7 D passive Drain of the N-channel MOSFET, tied internally with pins 5, 6 and 8; 30 V drain-source rating.
8 D passive Drain of the N-channel MOSFET, tied internally with pins 5, 6 and 7; 30 V drain-source rating.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDSS 30 V 2
Gate-Source Voltage VGSS -20 20 V 2
Drain Current (steady state) ID 8 A VGS = 10V, TA = +25°C, steady state 2
Drain Current (steady state) ID 6.4 A VGS = 10V, TA = +70°C, steady state 2
Drain Current (steady state) ID 6.7 A VGS = 4.5V, TA = +25°C, steady state 2
Drain Current (steady state) ID 5.3 A VGS = 4.5V, TA = +70°C, steady state 2
Pulsed Drain Current IDM 50 A Note 6: repetitive rating, pulse width limited by junction temperature 2
Total Power Dissipation PD 1.46 W Note 5: device mounted on FR-4 PCB, with minimum recommended pad layout 2
Drain-Source Breakdown Voltage BVDSS 30 V VGS = 0V, ID = 250μA 2
Zero Gate Voltage Drain Current IDSS 1 µA VDS = 30V, VGS = 0V 2
Gate-Source Leakage IGSS -100 100 nA VGS = ±20V, VDS = 0V 2
Gate Threshold Voltage VGS(th) 0.8 1.2 1.6 V VDS = VGS, ID = 250μA 2
Static Drain-Source On-Resistance RDS(on) 11 14 mΩ VGS = 10V, ID = 8A 2
Static Drain-Source On-Resistance RDS(on) 14 20 mΩ VGS = 4.5V, ID = 7A 2
Diode Forward Voltage VSD 0.72 0.94 V VGS = 0V, IS = 1A 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2
Thermal Resistance, Junction to Ambient RθJA 86 °C/W Note 5: device mounted on FR-4 PCB, with minimum recommended pad layout 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts Copper tin • Terminals Connections: See Diagram • Terminals: Finish - Matte Tin annealed over Copper leadframe. 1

CAD (KiCad official)

  • Symbol: DMN4800LSSL-13
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: dmn4800lssl-13-etched.step / dmn4800lssl-13-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dmn4800lssl-13.step / dmn4800lssl-13.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (7 pp, sha256 a919d6bf40e053c1, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF