component
DMN3067LW-7
Public Made by Adomby adom
Diodes Incorporated MOSFETs, SOT-323. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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dmn3067lw-7: specified limits as data (metadata.characteristics, 18 rows from the datasheet)
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DMN3067LW-7
Diodes Incorporated · MOSFETs · SOT-323
DMN3067LW-7 from Diodes Incorporated, in a SOT-323. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Gate | input | Gate control terminal rated for absolute maximum gate-source voltage ±12V with threshold voltage 0.5-1.5V at ID=250µA. |
| 2 | Source | passive | Source terminal serving as reference node for gate-source voltage measurement and drain current return path. |
| 3 | Drain | passive | Drain terminal rated for 30V drain-source breakdown voltage; conducts 2.6A maximum continuous current at VGS=4.5V and TA=+25°C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-323 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS | 30 | V | 2 | |||
| Gate-Source Voltage | VGSS | -12 | 12 | V | 2 | ||
| Continuous Drain Current | ID | 2.6 | A | VGS = 4.5V, steady state, TA = +25°C | 2 | ||
| Continuous Drain Current | ID | 2.1 | A | VGS = 4.5V, steady state, TA = +70°C | 2 | ||
| Pulsed Drain Current | IDM | 10 | A | 10µs pulse, duty cycle = 1% | 2 | ||
| Total Power Dissipation (Note 5) | PD | 0.5 | W | Note 5: FR-4 PC board, minimum recommended pad layout, single sided | 2 | ||
| Total Power Dissipation (Note 6) | PD | 1.1 | W | Note 6: FR-4 substrate PC board, 2oz copper, 1 inch square copper pad layout | 2 | ||
| Thermal Resistance, Junction to Ambient (Note 5) | RθJA | 241 | °C/W | Note 5: FR-4 PC board, minimum recommended pad layout, single sided | 2 | ||
| Thermal Resistance, Junction to Ambient (Note 6) | RθJA | 130 | °C/W | Note 6: FR-4 substrate PC board, 2oz copper, 1 inch square copper pad layout | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 | ||
| Drain-Source Breakdown Voltage | BVDSS | 30 | V | VGS = 0V, ID = 250μA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS = 30V, VGS = 0V | 2 | ||
| Gate-Body Leakage | IGSS | -10 | 10 | μA | VGS = ±12V, VDS = 0V | 2 | |
| Gate Threshold Voltage | VGS(th) | 0.5 | 1.5 | V | VDS = VGS, ID = 250μA | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 48 | 67 | mΩ | VGS = 4.5V, ID = 2.5A | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 50 | 70 | mΩ | VGS = 4.0V, ID = 2.5A | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 70 | 98 | mΩ | VGS = 2.5V, ID = 2.5A | 2 | |
| Diode Forward Voltage | VSD | 1.2 | V | VGS = 0V, IS = 0.6A | 2 |
CAD (KiCad official)
- Symbol:
DMN3067LW-7 - Footprint:
Package_TO_SOT_SMD:SOT-323_SC-70 - 3D model: SOT-323 (KiCad packages3D, STEP)
- 3D model files:
dmn3067lw-7-etched.step/dmn3067lw-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmn3067lw-7.step/dmn3067lw-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (6 pp, sha256
3c68ee4ed3e89a92, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DMN3067LW-7
**Diodes Incorporated** · MOSFETs · SOT-323
DMN3067LW-7 from Diodes Incorporated, in a SOT-323. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Gate | input | Gate control terminal rated for absolute maximum gate-source voltage ±12V with threshold voltage 0.5-1.5V at ID=250µA. |
| 2 | Source | passive | Source terminal serving as reference node for gate-source voltage measurement and drain current return path. |
| 3 | Drain | passive | Drain terminal rated for 30V drain-source breakdown voltage; conducts 2.6A maximum continuous current at VGS=4.5V and TA=+25°C. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-323 |
| Category | Transistors/Thyristors |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS | | | 30 | V | | 2 |
| Gate-Source Voltage | VGSS | -12 | | 12 | V | | 2 |
| Continuous Drain Current | ID | | | 2.6 | A | VGS = 4.5V, steady state, TA = +25°C | 2 |
| Continuous Drain Current | ID | | | 2.1 | A | VGS = 4.5V, steady state, TA = +70°C | 2 |
| Pulsed Drain Current | IDM | | | 10 | A | 10µs pulse, duty cycle = 1% | 2 |
| Total Power Dissipation (Note 5) | PD | | | 0.5 | W | Note 5: FR-4 PC board, minimum recommended pad layout, single sided | 2 |
| Total Power Dissipation (Note 6) | PD | | | 1.1 | W | Note 6: FR-4 substrate PC board, 2oz copper, 1 inch square copper pad layout | 2 |
| Thermal Resistance, Junction to Ambient (Note 5) | RθJA | | | 241 | °C/W | Note 5: FR-4 PC board, minimum recommended pad layout, single sided | 2 |
| Thermal Resistance, Junction to Ambient (Note 6) | RθJA | | | 130 | °C/W | Note 6: FR-4 substrate PC board, 2oz copper, 1 inch square copper pad layout | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 | | 150 | °C | | 2 |
| Drain-Source Breakdown Voltage | BVDSS | 30 | | | V | VGS = 0V, ID = 250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 1 | µA | VDS = 30V, VGS = 0V | 2 |
| Gate-Body Leakage | IGSS | -10 | | 10 | μA | VGS = ±12V, VDS = 0V | 2 |
| Gate Threshold Voltage | VGS(th) | 0.5 | | 1.5 | V | VDS = VGS, ID = 250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 48 | 67 | mΩ | VGS = 4.5V, ID = 2.5A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 50 | 70 | mΩ | VGS = 4.0V, ID = 2.5A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 70 | 98 | mΩ | VGS = 2.5V, ID = 2.5A | 2 |
| Diode Forward Voltage | VSD | | | 1.2 | V | VGS = 0V, IS = 0.6A | 2 |
## CAD (KiCad official)
- Symbol: `DMN3067LW-7`
- Footprint: `Package_TO_SOT_SMD:SOT-323_SC-70`
- 3D model: SOT-323 (KiCad packages3D, STEP)
- 3D model files: `dmn3067lw-7-etched.step` / `dmn3067lw-7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmn3067lw-7.step` / `dmn3067lw-7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885263309549568) (6 pp, sha256 `3c68ee4ed3e89a92`, retrieved 2026-09-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dmn3067lw-7-datasheet.pdf)