# DMG1016UDW-7

**Diodes Incorporated** · MOSFETs · SOT-363

DMG1016UDW-7 from Diodes Incorporated, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of N-channel MOSFET Q1 (BVDSS 20V, 1066mA at TA=+25°C). |
| 2 | G1 | input | Gate of N-channel Q1, ESD protected, with VGSS of ±6V maximum and threshold VGS(TH) of 0.5 to 1.0V. |
| 3 | D2 | passive | Drain of P-channel MOSFET Q2 (BVDSS -20V, -845mA at TA=+25°C). |
| 4 | S2 | passive | Source of P-channel MOSFET Q2. |
| 5 | G2 | input | Gate of P-channel Q2, ESD protected, with VGSS of ±6V maximum and threshold VGS(TH) of -0.5 to -1.0V. |
| 6 | D1 | passive | Drain of N-channel MOSFET Q1 (BVDSS 20V, 1066mA at TA=+25°C). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-363 |
| Category | Transistors |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage (Q1 N-ch) | BVDSS | 20 |  |  | V | VGS = 0V, ID = 250μA | 3 |
| Zero Gate Voltage Drain Current (Q1 N-ch) | IDSS |  |  | 100 | nA | @TC = +25°C; VDS = 20V, VGS = 0V | 3 |
| Gate-Source Leakage (Q1 N-ch) | IGSS | -1 |  | 1 | μA | VGS = ±4.5V, VDS = 0V | 3 |
| Gate Threshold Voltage (Q1 N-ch) | VGS(TH) | 0.5 |  | 1 | V | VDS = VGS, ID = 250μA | 3 |
| Static Drain-Source On-Resistance (Q1 N-ch) | RDS(ON) |  | 0.3 | 0.45 | Ω | VGS = 4.5V, ID = 600mA | 3 |
| Static Drain-Source On-Resistance (Q1 N-ch) | RDS(ON) |  | 0.4 | 0.6 | Ω | VGS = 2.5V, ID = 500mA | 3 |
| Static Drain-Source On-Resistance (Q1 N-ch) | RDS(ON) |  | 0.5 | 0.75 | Ω | VGS = 1.8V, ID = 350mA | 3 |
| Diode Forward Voltage (Q1 N-ch) | VSD |  | 0.7 | 1.2 | V | VGS = 0V, IS = 150mA | 3 |
| Drain-Source Breakdown Voltage (Q2 P-ch) | BVDSS | -20 |  |  | V | VGS = 0V, ID = -250μA | 7 |
| Zero Gate Voltage Drain Current (Q2 P-ch) | IDSS |  |  | -100 | nA | @TC = +25°C; VDS = -20V, VGS = 0V | 7 |
| Gate-Source Leakage (Q2 P-ch) | IGSS | -2 |  | 2 | μA | VGS = ±4.5V, VDS = 0V | 7 |
| Gate Threshold Voltage (Q2 P-ch) | VGS(TH) | -0.5 |  | -1 | V | VDS = VGS, ID = -250μA | 7 |
| Static Drain-Source On-Resistance (Q2 P-ch) | RDS(ON) |  | 0.5 | 0.75 | Ω | VGS = -4.5V, ID = -430mA | 7 |
| Static Drain-Source On-Resistance (Q2 P-ch) | RDS(ON) |  | 0.7 | 1.05 | Ω | VGS = -2.5V, ID = -300mA | 7 |
| Static Drain-Source On-Resistance (Q2 P-ch) | RDS(ON) |  | 1 | 1.5 | Ω | VGS = -1.8V, ID = -150mA | 7 |
| Diode Forward Voltage (Q2 P-ch) | VSD |  | -0.8 | -1.2 | V | VGS = 0V, IS = -150mA | 7 |
| Drain-Source Voltage (Q1 N-ch) | VDSS |  |  | 20 | V | @TA = +25°C | 2 |
| Gate-Source Voltage (Q1 N-ch) | VGSS | -6 |  | 6 | V | @TA = +25°C | 2 |
| Continuous Drain Current, steady state (Q1 N-ch) | ID |  |  | 1066 | mA | Steady state, TA = +25°C; Note 5 | 2 |
| Continuous Drain Current, steady state (Q1 N-ch) | ID |  |  | 690 | mA | Steady state, TA = +85°C; Note 5 | 2 |
| Pulsed Drain Current (Q1 N-ch) | IDM |  |  | 3.2 | A | 10μs pulse, duty cycle = 1% | 2 |
| Drain-Source Voltage (Q2 P-ch) | VDSS | -20 |  |  | V | @TA = +25°C | 2 |
| Gate-Source Voltage (Q2 P-ch) | VGSS | -6 |  | 6 | V | @TA = +25°C | 2 |
| Continuous Drain Current, steady state (Q2 P-ch) | ID | -845 |  |  | mA | Steady state, TA = +25°C; Note 5 | 2 |
| Continuous Drain Current, steady state (Q2 P-ch) | ID | -548 |  |  | mA | Steady state, TA = +85°C; Note 5 | 2 |
| Pulsed Drain Current (Q2 P-ch) | IDM | -2.2 |  |  | A | 10μs pulse, duty cycle = 1% | 2 |
| Total Power Dissipation | PD |  |  | 330 | mW | Note 5: device mounted on FR-4 PCB with minimum recommended pad layout | 2 |
| Thermal Resistance, Junction to Ambient | RθJA |  |  | 379 | °C/W | Note 5: device mounted on FR-4 PCB with minimum recommended pad layout | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 150 | °C |  | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin |  Terminals: Matte Tin Finish Annealed over Alloy 42 Leadframe (Lead Free Plating). Solderable per MIL-STD-202, Method 208 | 1 |

## CAD (KiCad official)

- Symbol: `DMG1016UDW-7`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files: `dmg1016udw-7-etched.step` / `dmg1016udw-7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmg1016udw-7.step` / `dmg1016udw-7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Diodes Incorporated datasheet](https://www.diodes.com/assets/Datasheets/DMG1016UDW-7.pdf) (12 pp, sha256 `f4f9b0468036d46f`, retrieved 2026-11-04, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dmg1016udw-7-datasheet.pdf)