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DMC6040SSDQ-13

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Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DMC6040SSDQ-13

Diodes Incorporated · MOSFETs · SO-8

DMC6040SSDQ-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of Q1 N-channel MOSFET (60V VDSS, 6.5A max ID at t<10s).
2 G1 input Gate of Q1 N-channel MOSFET, rated for VGSS of ±20V.
3 S2 passive Source of Q2 P-channel MOSFET (-60V VDSS, -3.9A max ID at t<10s).
4 G2 input Gate of Q2 P-channel MOSFET, rated for VGSS of ±20V.
5 D2 passive Drain of Q2 P-channel MOSFET, tied internally to pin 6 (-60V VDSS).
6 D2 passive Drain of Q2 P-channel MOSFET, tied internally to pin 5 (-60V VDSS).
7 D1 passive Drain of Q1 N-channel MOSFET, tied internally to pin 8 (60V VDSS).
8 D1 passive Drain of Q1 N-channel MOSFET, tied internally to pin 7 (60V VDSS).

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Q1 Drain-Source Voltage VDSS 60 V TA = +25°C 2
Q2 Drain-Source Voltage VDSS -60 V TA = +25°C 2
Q1 Gate-Source Voltage VGSS -20 20 V TA = +25°C 2
Q2 Gate-Source Voltage VGSS -20 20 V TA = +25°C 2
Q1 Continuous Drain Current steady state ID 5.1 A VGS = 10V, Steady State, TA = +25°C (Note 7) 2
Q1 Continuous Drain Current t<10s ID 6.5 A t<10s, TA = +25°C (Note 7) 2
Q2 Continuous Drain Current steady state ID -3.1 A Steady State, TA = +25°C (Note 7) 2
Q2 Continuous Drain Current t<10s ID -3.9 A t<10s, TA = +25°C (Note 7) 2
Q1 Maximum Body Diode Forward Current IS 2.1 A Note 7 2
Q2 Maximum Body Diode Forward Current IS -2.1 A Note 7 2
Q1 Pulsed Drain Current IDM 28 A 10µs Pulse, Duty Cycle = 1% 2
Q2 Pulsed Drain Current IDM -19 A 10µs Pulse, Duty Cycle = 1% 2
Q1 Avalanche Current IAS 17.2 A L = 0.1mH (Note 8) 2
Q2 Avalanche Current IAS -17.6 A L = 0.1mH (Note 8) 2
Q1 Avalanche Energy EAS 14.7 mJ L = 0.1mH (Note 8) 2
Q2 Avalanche Energy EAS 15.4 mJ L = 0.1mH (Note 8) 2
Total Power Dissipation (Note 6) PD 1.24 W TA = +25°C 2
Total Power Dissipation (Note 7) PD 1.56 W TA = +25°C 2
Thermal Resistance Junction to Ambient steady state (Note 6) RθJA 101 °C/W Steady State 2
Thermal Resistance Junction to Ambient t<10s (Note 6) RθJA 61 °C/W t < 10s 2
Thermal Resistance Junction to Ambient steady state (Note 7) RθJA 80 °C/W Steady State 2
Thermal Resistance Junction to Ambient t<10s (Note 7) RθJA 49 °C/W t<10s 2
Thermal Resistance Junction to Case (Note 7) RθJC 14.7 °C/W 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2
Q1 Drain-Source Breakdown Voltage BVDSS 60 V VGS = 0V, ID = 250µA 2
Q1 Zero Gate Voltage Drain Current IDSS 1 µA VDS = 48V, VGS = 0V 2
Q1 Gate-Source Leakage IGSS 100 nA VGS = 20V, VDS = 0V 2
Q1 Gate Threshold Voltage VGS(TH) 1 3 V VDS = VGS, ID = 250µA 2
Q1 Static Drain-Source On-Resistance (10V) RDS(ON) 33 40 mΩ VGS = 10V, ID = 8A 2
Q1 Static Drain-Source On-Resistance (4.5V) RDS(ON) 37 55 mΩ VGS = 4.5V, ID = 5A 2
Q1 Diode Forward Voltage VSD 0.7 1.2 V VGS = 0V, IS = 1A 2
Q2 Drain-Source Breakdown Voltage BVDSS -60 V VGS = 0V, ID = -250µA 5
Q2 Zero Gate Voltage Drain Current IDSS -1 µA VDS = -48V, VGS = 0V 5
Q2 Gate-Source Leakage IGSS 100 nA VGS = ±16V, VDS = 0V 5
Q2 Gate Threshold Voltage VGS(TH) -1 -3 V VDS = VGS, ID = -250µA 5
Q2 Static Drain-Source On-Resistance (-10V) RDS(ON) 91 110 mΩ VGS = -10V, ID = -4.5A 5
Q2 Static Drain-Source On-Resistance (-4.5V) RDS(ON) 110 130 mΩ VGS = -4.5V, ID =-3.5A 5
Q2 Diode Forward Voltage VSD -0.7 -1.2 V VGS = 0V, IS = -1A 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC Body Diode Reverse Recovery Charge QRR  7.5  nC IS = 4.3A, dI/dt = 100A/μs Notes: 6. Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. 2
contacts Copper tin  Terminal Connections: See Diagram  Terminals: Finish, Tin Finish Annealed over Copper Leadframe. 1

CAD (KiCad official)

  • Symbol: DMC6040SSDQ-13
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: dmc6040ssdq-13-etched.step / dmc6040ssdq-13-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dmc6040ssdq-13.step / dmc6040ssdq-13.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (9 pp, sha256 3ec2f8689453f3c5, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF