component

DMC4028SSD-VB

Public Made by Adom

by adom

VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttriode-mos tube-transistordmc4028ssd-vbfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 12d ago
viewers dmc4028ssd-vb: viewers · Ray 12d ago
dmc4028ssd-vb-etched.glb Publish 0.1.0 · Ray 12d ago
dmc4028ssd-vb-etched.step dmc4028ssd-vb: factory component page (tier=lcsc) · Ray 12d ago
dmc4028ssd-vb-hero.glb dmc4028ssd-vb: hero GLB from the etched model (keeps the MPN mark) · Ray 12d ago
dmc4028ssd-vb-hero.overlay.json Publish 0.1.0 · Ray 12d ago
dmc4028ssd-vb.glb Publish 0.1.0 · Ray 12d ago
dmc4028ssd-vb.kicad_mod Publish 0.1.0 · Ray 12d ago
dmc4028ssd-vb.kicad_sym Publish 0.1.0 · Ray 12d ago
dmc4028ssd-vb.lbr Publish 0.1.0 · Ray 12d ago
dmc4028ssd-vb.step Publish 0.1.0 · Ray 12d ago
package.json Publish 0.1.0 · Ray 12d ago
page.json Set visibility: public · Ray 12d ago
README.md Publish 0.1.0 · Ray 12d ago

DMC4028SSD-VB

VBsemi Elec · MOSFETs · SO-8

DMC4028SSD-VB from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of the N-channel MOSFET (60 V VDS, 5.3 A at TC = 25 °C).
2 G1 input Gate of the N-channel MOSFET, rated at ±20 V VGS maximum.
3 S2 passive Source of the P-channel MOSFET (-60 V VDS).
4 G2 input Gate of the P-channel MOSFET, rated at ±20 V VGS maximum.
5 D2 passive Drain of the P-channel MOSFET (-60 V VDS), internally common with pin 6.
6 D2 passive Drain of the P-channel MOSFET (-60 V VDS), internally common with pin 5.
7 D1 passive Drain of the N-channel MOSFET (60 V VDS), internally common with pin 8.
8 D1 passive Drain of the N-channel MOSFET (60 V VDS), internally common with pin 7.

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package SO-8
Category Triode/MOS Tube/Transistor
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
N-Ch Drain-Source Voltage VDS 60 V N-Channel, TA = 25 °C 1
P-Ch Drain-Source Voltage VDS -60 V P-Channel, TA = 25 °C 1
Gate-Source Voltage VGS -20 20 V TA = 25 °C 1
N-Ch Pulsed Drain Current IDM 20 A N-Channel, 10 µs pulse width 1
P-Ch Pulsed Drain Current IDM -25 A P-Channel, 10 µs pulse width 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
N-Ch Single Pulse Avalanche Current IAS 11 A N-Channel, L = 0.1 mH 1
P-Ch Single Pulse Avalanche Current IAS 15 A P-Channel, L = 0.1 mH 1
N-Ch Maximum Junction-to-Ambient RthJA 55 62.5 °C/W N-Channel, t ≤ 10 s 1
P-Ch Maximum Junction-to-Ambient RthJA 53 62.5 °C/W P-Channel, t ≤ 10 s 1
N-Ch Maximum Junction-to-Foot (Drain) RthJF 33 40 °C/W N-Channel, Steady State 1
P-Ch Maximum Junction-to-Foot (Drain) RthJF 30 37 °C/W P-Channel, Steady State 1
N-Ch Drain-Source Breakdown Voltage VDS 60 V VGS = 0 V, ID = 250 µA 2
P-Ch Drain-Source Breakdown Voltage VDS -60 V VGS = 0 V, ID = - 250 µA 2
N-Ch Gate Threshold Voltage VGS(th) 1 3 V VDS = VGS, ID = 250 µA 2
P-Ch Gate Threshold Voltage VGS(th) -1 -3 V VDS = VGS, ID = - 250 µA 2
N-Ch Gate-Body Leakage IGSS 100 nA VDS = 0 V, VGS = ± 20 V 2
P-Ch Gate-Body Leakage IGSS -100 nA VDS = 0 V, VGS = ± 20 V 2
N-Ch Zero Gate Voltage Drain Current IDSS 1 µA VDS = 60 V, VGS = 0 V 2
P-Ch Zero Gate Voltage Drain Current IDSS -1 µA VDS = - 60 V, VGS = 0 V 2
N-Ch Zero Gate Voltage Drain Current IDSS 10 µA VDS = 60 V, VGS = 0 V, TJ = 55 °C 2
P-Ch Zero Gate Voltage Drain Current IDSS -10 µA VDS = - 60 V, VGS = 0 V, TJ = 55 °C 2
N-Ch On-State Drain Current ID(on) 20 A VDS ≥ 5 V, VGS = 10 V 2
P-Ch On-State Drain Current ID(on) -25 A VDS ≤ - 5 V, VGS = - 10 V 2
N-Ch Total Gate Charge Qg 13 20 nC VDS = 30 V, VGS = 10 V, ID = 4.3 A 2
P-Ch Total Gate Charge Qg 14.5 22 nC VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A 2
N-Ch Total Gate Charge Qg 6 9 nC VDS = 30 V, VGS = 4.5 V, ID = 4.3 A 2
P-Ch Total Gate Charge Qg 8 12 nC VDS = - 30 V, VGS = - 4.5 V, ID = - 3.1 A 2
N-Ch Gate Resistance Rg 2 3 Ω f = 1 MHz 2
P-Ch Gate Resistance Rg 14 20 Ω f = 1 MHz 2
N-Ch Turn-On Delay Time td(on) 15 25 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω 3
P-Ch Turn-On Delay Time td(on) 30 45 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 4.5 V, Rg = 1 Ω 3
N-Ch Rise Time tr 65 100 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω 3
P-Ch Rise Time tr 70 105 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 4.5 V, Rg = 1 Ω 3
N-Ch Turn-Off Delay Time td(off) 15 25 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω 3
P-Ch Turn-Off Delay Time td(off) 40 60 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 4.5 V, Rg = 1 Ω 3
N-Ch Fall Time tf 10 15 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω 3
P-Ch Fall Time tf 30 45 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 4.5 V, Rg = 1 Ω 3
N-Ch Turn-On Delay Time td(on) 10 15 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 10 V, Rg = 1 Ω 3
P-Ch Turn-On Delay Time td(on) 10 15 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 10 V, Rg = 1 Ω 3
N-Ch Rise Time tr 15 25 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 10 V, Rg = 1 Ω 3
P-Ch Rise Time tr 13 20 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 10 V, Rg = 1 Ω 3
N-Ch Turn-Off Delay Time td(off) 20 30 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 10 V, Rg = 1 Ω 3
P-Ch Turn-Off Delay Time td(off) 35 55 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 10 V, Rg = 1 Ω 3
N-Ch Body Diode Voltage VSD 0.8 1.2 V IS = 1.7 A 3
P-Ch Body Diode Voltage VSD -0.8 -1.2 V IS = - 2 A 3
N-Ch Body Diode Reverse Recovery Time trr 30 60 ns IF = 1.7 A, dI/dt = 100 A/µs, TJ = 25 °C 3
P-Ch Body Diode Reverse Recovery Time trr 30 50 ns IF = - 2 A, dI/dt = - 100 A/µs, TJ = 25 °C 3
N-Ch Body Diode Reverse Recovery Charge Qrr 32 50 nC IF = 1.7 A, dI/dt = 100 A/µs, TJ = 25 °C 3
P-Ch Body Diode Reverse Recovery Charge Qrr 35 60 nC IF = - 2 A, dI/dt = - 100 A/µs, TJ = 25 °C 3
N-Ch Drain-Source On-State Resistance RDS(on) 0.029 Ω VGS = 4.5 V, ID = 3.9 A 2
P-Ch Drain-Source On-State Resistance RDS(on) 0.055 Ω VGS = - 10 V, ID = - 3.1 A 2
P-Ch Drain-Source On-State Resistance RDS(on) 0.06 Ω VGS = - 4.5 V, ID = - 0.2 A 2
N-Ch Forward Transconductance gfs 15 S VDS = 15 V, ID = 4.3 A 2
P-Ch Forward Transconductance gfs 8.5 S VDS = - 15 V, ID = - 3.1 A 2
N-Ch Input Capacitance Ciss 665 pF VDS = 15 V, VGS = 0 V, f = 1 MHz 2
P-Ch Input Capacitance Ciss 650 pF VDS = - 15 V, VGS = 0 V, f = 1 MHz 2

CAD (KiCad official)

  • Symbol: DMC4028SSD-VB
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: dmc4028ssd-vb-etched.step / dmc4028ssd-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dmc4028ssd-vb.step / dmc4028ssd-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (14 pp, sha256 dd38806e40944570, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF