component
DMC2710UV-7
Public Made by Adomby adom
Diodes Incorporated MOSFETs, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DMC2710UV-7
Diodes Incorporated · MOSFETs · SOT-563
DMC2710UV-7 from Diodes Incorporated, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of N-channel MOSFET Q1 (BVDSS 20V, ID 1.1A at TA=+25°C). |
| 2 | G1 | input | Gate of N-channel MOSFET Q1, ESD protected with gate protection diode, VGSS ±6V, VGS(TH) 0.5 to 1.0V. |
| 3 | D2 | passive | Drain of P-channel MOSFET Q2 (BVDSS -20V, ID -0.8A at TA=+25°C). |
| 4 | S2 | passive | Source of P-channel MOSFET Q2. |
| 5 | G2 | input | Gate of P-channel MOSFET Q2, ESD protected with gate protection diode, VGSS ±6V, VGS(TH) -0.5 to -1.0V. |
| 6 | D1 | passive | Drain of N-channel MOSFET Q1, VDSS 20V, pulsed drain current IDM 5A. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-563 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage, Q1 N-Channel | VDSS | 20 | V | 2 | |||
| Drain-Source Voltage, Q2 P-Channel | VDSS | -20 | V | 2 | |||
| Gate-Source Voltage, Q1 N-Channel | VGSS | -6 | 6 | V | 2 | ||
| Gate-Source Voltage, Q2 P-Channel | VGSS | -6 | 6 | V | 2 | ||
| Continuous Drain Current, Q1 N-Channel, steady state | ID | 1.1 | A | Steady State TA = +25°C; N-Channel VGS = 4.5V | 2 | ||
| Continuous Drain Current, Q1 N-Channel, steady state | ID | 0.9 | A | Steady State TA = +70°C; N-Channel VGS = 4.5V | 2 | ||
| Continuous Drain Current, Q2 P-Channel, steady state | ID | -0.8 | A | Steady State TA = +25°C; P-Channel VGS = -4.5V | 2 | ||
| Continuous Drain Current, Q2 P-Channel, steady state | ID | -0.7 | A | Steady State TA = +70°C; P-Channel VGS = -4.5V | 2 | ||
| Maximum Continuous Body Diode Forward Current, Q1 N-Channel | IS | 0.9 | A | Note 6 | 2 | ||
| Maximum Continuous Body Diode Forward Current, Q2 P-Channel | IS | -0.9 | A | Note 6 | 2 | ||
| Pulsed Drain Current, Q1 N-Channel | IDM | 5 | A | 10µs Pulse, Duty Cycle = 1% | 2 | ||
| Pulsed Drain Current, Q2 P-Channel | IDM | -3 | A | 10µs Pulse, Duty Cycle = 1% | 2 | ||
| Total Power Dissipation | PD | 0.46 | W | TA = +25°C; Note 5 (FR-4, minimum recommended pad layout) | 2 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 274 | °C/W | Steady State; Note 5 (FR-4, minimum recommended pad layout) | 2 | ||
| Total Power Dissipation | PD | 0.8 | W | TA = +25°C; Note 6 (FR-4, 1 inch square copper plate) | 2 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 152 | °C/W | Steady State; Note 6 (FR-4, 1 inch square copper plate) | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 | ||
| Drain-Source Breakdown Voltage, Q1 N-Channel | BVDSS | 20 | V | VGS = 0V, ID = 250µA | 2 | ||
| Zero Gate Voltage Drain Current @TC = +25°C, Q1 N-Channel | IDSS | 100 | nA | VDS = 20V, VGS = 0V | 2 | ||
| Gate-Source Leakage, Q1 N-Channel | IGSS | -1 | 1 | μA | VGS = ±4.5V, VDS = 0V | 2 | |
| Gate Threshold Voltage, Q1 N-Channel | VGS(TH) | 0.5 | 0.88 | 1 | V | VDS = VGS, ID = 250μA | 2 |
| Static Drain-Source On-Resistance, Q1 N-Channel | RDS(ON) | 0.14 | 0.4 | Ω | VGS = 4.5V, ID = 600mA | 2 | |
| Static Drain-Source On-Resistance, Q1 N-Channel | RDS(ON) | 0.18 | 0.5 | Ω | VGS = 2.5V, ID = 500mA | 2 | |
| Static Drain-Source On-Resistance, Q1 N-Channel | RDS(ON) | 0.28 | 0.7 | Ω | VGS = 1.8V, ID = 350mA | 2 | |
| Diode Forward Voltage, Q1 N-Channel | VSD | 0.7 | 1.2 | V | VGS = 0V, IS = 150mA | 2 | |
| Drain-Source Breakdown Voltage, Q2 P-Channel | BVDSS | -20 | V | VGS = 0V, ID = -250μA | 3 | ||
| Zero Gate Voltage Drain Current @TC = +25°C, Q2 P-Channel | IDSS | -100 | nA | VDS = -20V, VGS = 0V | 3 | ||
| Gate-Source Leakage, Q2 P-Channel | IGSS | -2 | 2 | μA | VGS = ±4.5V, VDS = 0V | 3 | |
| Gate Threshold Voltage, Q2 P-Channel | VGS(TH) | -0.5 | -0.8 | -1 | V | VDS = VGS, ID = -250μA | 3 |
| Static Drain-Source On-Resistance, Q2 P-Channel | RDS(ON) | 0.4 | 0.7 | Ω | VGS = -4.5V, ID = -430mA | 3 | |
| Static Drain-Source On-Resistance, Q2 P-Channel | RDS(ON) | 0.5 | 0.9 | Ω | VGS = -2.5V, ID = -300mA | 3 | |
| Static Drain-Source On-Resistance, Q2 P-Channel | RDS(ON) | 0.7 | 1.3 | Ω | VGS = -1.8V, ID = -150mA | 3 | |
| Diode Forward Voltage, Q2 P-Channel | VSD | -0.7 | -1.2 | V | VGS = 0V, IS = -150mA | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | Terminal Connections: See Diagram Terminals: Finish, Matte Tin Annealed over Copper Leadframe. | 1 |
CAD (KiCad official)
- Symbol:
DMC2710UV-7 - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files:
dmc2710uv-7-etched.step/dmc2710uv-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmc2710uv-7.step/dmc2710uv-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (10 pp, sha256
869a64f739ff24c2, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DMC2710UV-7
**Diodes Incorporated** · MOSFETs · SOT-563
DMC2710UV-7 from Diodes Incorporated, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of N-channel MOSFET Q1 (BVDSS 20V, ID 1.1A at TA=+25°C). |
| 2 | G1 | input | Gate of N-channel MOSFET Q1, ESD protected with gate protection diode, VGSS ±6V, VGS(TH) 0.5 to 1.0V. |
| 3 | D2 | passive | Drain of P-channel MOSFET Q2 (BVDSS -20V, ID -0.8A at TA=+25°C). |
| 4 | S2 | passive | Source of P-channel MOSFET Q2. |
| 5 | G2 | input | Gate of P-channel MOSFET Q2, ESD protected with gate protection diode, VGSS ±6V, VGS(TH) -0.5 to -1.0V. |
| 6 | D1 | passive | Drain of N-channel MOSFET Q1, VDSS 20V, pulsed drain current IDM 5A. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-563 |
| Category | Transistors/Thyristors |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage, Q1 N-Channel | VDSS | | | 20 | V | | 2 |
| Drain-Source Voltage, Q2 P-Channel | VDSS | | | -20 | V | | 2 |
| Gate-Source Voltage, Q1 N-Channel | VGSS | -6 | | 6 | V | | 2 |
| Gate-Source Voltage, Q2 P-Channel | VGSS | -6 | | 6 | V | | 2 |
| Continuous Drain Current, Q1 N-Channel, steady state | ID | | | 1.1 | A | Steady State TA = +25°C; N-Channel VGS = 4.5V | 2 |
| Continuous Drain Current, Q1 N-Channel, steady state | ID | | | 0.9 | A | Steady State TA = +70°C; N-Channel VGS = 4.5V | 2 |
| Continuous Drain Current, Q2 P-Channel, steady state | ID | | | -0.8 | A | Steady State TA = +25°C; P-Channel VGS = -4.5V | 2 |
| Continuous Drain Current, Q2 P-Channel, steady state | ID | | | -0.7 | A | Steady State TA = +70°C; P-Channel VGS = -4.5V | 2 |
| Maximum Continuous Body Diode Forward Current, Q1 N-Channel | IS | | | 0.9 | A | Note 6 | 2 |
| Maximum Continuous Body Diode Forward Current, Q2 P-Channel | IS | | | -0.9 | A | Note 6 | 2 |
| Pulsed Drain Current, Q1 N-Channel | IDM | | | 5 | A | 10µs Pulse, Duty Cycle = 1% | 2 |
| Pulsed Drain Current, Q2 P-Channel | IDM | | | -3 | A | 10µs Pulse, Duty Cycle = 1% | 2 |
| Total Power Dissipation | PD | | | 0.46 | W | TA = +25°C; Note 5 (FR-4, minimum recommended pad layout) | 2 |
| Thermal Resistance, Junction to Ambient | RθJA | | | 274 | °C/W | Steady State; Note 5 (FR-4, minimum recommended pad layout) | 2 |
| Total Power Dissipation | PD | | | 0.8 | W | TA = +25°C; Note 6 (FR-4, 1 inch square copper plate) | 2 |
| Thermal Resistance, Junction to Ambient | RθJA | | | 152 | °C/W | Steady State; Note 6 (FR-4, 1 inch square copper plate) | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 | | 150 | °C | | 2 |
| Drain-Source Breakdown Voltage, Q1 N-Channel | BVDSS | 20 | | | V | VGS = 0V, ID = 250µA | 2 |
| Zero Gate Voltage Drain Current @TC = +25°C, Q1 N-Channel | IDSS | | | 100 | nA | VDS = 20V, VGS = 0V | 2 |
| Gate-Source Leakage, Q1 N-Channel | IGSS | -1 | | 1 | μA | VGS = ±4.5V, VDS = 0V | 2 |
| Gate Threshold Voltage, Q1 N-Channel | VGS(TH) | 0.5 | 0.88 | 1 | V | VDS = VGS, ID = 250μA | 2 |
| Static Drain-Source On-Resistance, Q1 N-Channel | RDS(ON) | | 0.14 | 0.4 | Ω | VGS = 4.5V, ID = 600mA | 2 |
| Static Drain-Source On-Resistance, Q1 N-Channel | RDS(ON) | | 0.18 | 0.5 | Ω | VGS = 2.5V, ID = 500mA | 2 |
| Static Drain-Source On-Resistance, Q1 N-Channel | RDS(ON) | | 0.28 | 0.7 | Ω | VGS = 1.8V, ID = 350mA | 2 |
| Diode Forward Voltage, Q1 N-Channel | VSD | | 0.7 | 1.2 | V | VGS = 0V, IS = 150mA | 2 |
| Drain-Source Breakdown Voltage, Q2 P-Channel | BVDSS | -20 | | | V | VGS = 0V, ID = -250μA | 3 |
| Zero Gate Voltage Drain Current @TC = +25°C, Q2 P-Channel | IDSS | | | -100 | nA | VDS = -20V, VGS = 0V | 3 |
| Gate-Source Leakage, Q2 P-Channel | IGSS | -2 | | 2 | μA | VGS = ±4.5V, VDS = 0V | 3 |
| Gate Threshold Voltage, Q2 P-Channel | VGS(TH) | -0.5 | -0.8 | -1 | V | VDS = VGS, ID = -250μA | 3 |
| Static Drain-Source On-Resistance, Q2 P-Channel | RDS(ON) | | 0.4 | 0.7 | Ω | VGS = -4.5V, ID = -430mA | 3 |
| Static Drain-Source On-Resistance, Q2 P-Channel | RDS(ON) | | 0.5 | 0.9 | Ω | VGS = -2.5V, ID = -300mA | 3 |
| Static Drain-Source On-Resistance, Q2 P-Channel | RDS(ON) | | 0.7 | 1.3 | Ω | VGS = -1.8V, ID = -150mA | 3 |
| Diode Forward Voltage, Q2 P-Channel | VSD | | -0.7 | -1.2 | V | VGS = 0V, IS = -150mA | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin | Terminal Connections: See Diagram Terminals: Finish, Matte Tin Annealed over Copper Leadframe. | 1 |
## CAD (KiCad official)
- Symbol: `DMC2710UV-7`
- Footprint: `Package_TO_SOT_SMD:SOT-563`
- 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files: `dmc2710uv-7-etched.step` / `dmc2710uv-7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmc2710uv-7.step` / `dmc2710uv-7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603008188321185792) (10 pp, sha256 `869a64f739ff24c2`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dmc2710uv-7-datasheet.pdf)