# DMC2053UVT-7

**Diodes Incorporated** · MOSFETs · TSOT-26

DMC2053UVT-7 from Diodes Incorporated, in a TSOT-26. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D1 | passive | Drain of the N-channel MOSFET Q1, rated for BVDSS 20V with continuous ID of 4.6A at TA=+25°C. |
| 2 | S1 | passive | Source of the N-channel MOSFET Q1, paired with D1 in the complementary dual-MOSFET package. |
| 3 | D2 | passive | Drain of the P-channel MOSFET Q2, rated for BVDSS -20V with continuous ID of -3.2A at TA=+25°C. |
| 4 | G2 | input | Gate of the P-channel MOSFET Q2, driven relative to S2 (pin 5). |
| 5 | S2 | passive | Source of the P-channel MOSFET Q2, paired with D2 (pin 3) and G2 (pin 4). |
| 6 | G1 | input | Gate of the N-channel MOSFET Q1, driven relative to S1 (pin 2). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | TSOT-26 |
| Category | Transistors/Thyristors |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage (Q1 N-Channel) | VDSS |  |  | 20 | V |  | 2 |
| Drain-Source Voltage (Q2 P-Channel) | VDSS | -20 |  |  | V |  | 2 |
| Gate-Source Voltage (Q1 N-Channel) | VGSS | -12 |  | 12 | V |  | 2 |
| Gate-Source Voltage (Q2 P-Channel) | VGSS | -12 |  | 12 | V |  | 2 |
| Continuous Drain Current (Q1 N-Channel) | ID |  |  | 4.6 | A | VGS = 4.5V, Steady State, TA = +25°C (Note 6) | 2 |
| Continuous Drain Current (Q1 N-Channel) | ID |  |  | 3.7 | A | VGS = 4.5V, Steady State, TA = +70°C (Note 6) | 2 |
| Continuous Drain Current (Q2 P-Channel) | ID | -3.2 |  |  | A | VGS = 4.5V, Steady State, TA = +25°C (Note 6) | 2 |
| Continuous Drain Current (Q2 P-Channel) | ID | -2.6 |  |  | A | VGS = 4.5V, Steady State, TA = +70°C (Note 6) | 2 |
| Maximum Continuous Body Diode Forward Current (Q1 N-Channel) | IS |  |  | 1.4 | A | Note 6 | 2 |
| Maximum Continuous Body Diode Forward Current (Q2 P-Channel) | IS | -1.3 |  |  | A | Note 6 | 2 |
| Pulsed Drain Current (Q1 N-Channel) | IDM |  |  | 22 | A | 10µs Pulse, Duty Cycle = 1% | 2 |
| Pulsed Drain Current (Q2 P-Channel) | IDM | -20 |  |  | A | 10µs Pulse, Duty Cycle = 1% | 2 |
| Total Power Dissipation | PD |  |  | 0.7 | W | TA = +25°C (Note 5) | 2 |
| Total Power Dissipation | PD |  |  | 1.1 | W | TA = +25°C (Note 6) | 2 |
| Thermal Resistance, Junction to Ambient | RθJA |  |  | 173 | °C/W | Steady State (Note 5) | 2 |
| Thermal Resistance, Junction to Ambient | RθJA |  |  | 108 | °C/W | Steady State (Note 6) | 2 |
| Thermal Resistance, Junction to Case | RθJC |  |  | 37 |  |  | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 150 | °C |  | 2 |
| Drain-Source Breakdown Voltage (Q1 N-Channel) | BVDSS | 20 |  |  | V | VGS = 0V, ID = 250µA | 2 |
| Gate Threshold Voltage (Q1 N-Channel) | VGS(TH) | 0.4 |  | 1 | V | VDS = VGS, ID = 250μA | 2 |
| Gate-Source Leakage (Q1 N-Channel) | IGSS | -100 |  | 100 | nA | VGS = ±12V, VDS = 0V | 2 |
| Zero Gate Voltage Drain Current (Q1 N-Channel) | IDSS |  |  | 1 | µA | VDS = 20V, VGS = 0V | 2 |
| Static Drain-Source On-Resistance (Q1 N-Channel) | RDS(ON) |  |  | 35 | mΩ | VGS = 4.5V, ID = 5.0A | 2 |
| Static Drain-Source On-Resistance (Q1 N-Channel) | RDS(ON) |  |  | 43 | mΩ | VGS = 2.5V, ID = 4.0A | 2 |
| Static Drain-Source On-Resistance (Q1 N-Channel) | RDS(ON) |  |  | 56 | mΩ | VGS = 1.8V, ID = 2.0A | 2 |
| Diode Forward Voltage (Q1 N-Channel) | VSD |  | 0.7 | 1.2 | V | VGS = 0V, IS = 1A | 2 |
| Drain-Source Breakdown Voltage (Q2 P-Channel) | BVDSS | -20 |  |  | V | VGS = 0V, ID = -250µA | 3 |
| Gate Threshold Voltage (Q2 P-Channel) | VGS(TH) | -0.45 |  | -1 | V | VDS = VGS, ID = -250μA | 3 |
| Gate-Source Leakage (Q2 P-Channel) | IGSS | -100 |  | 100 | nA | VGS = ±12V, VDS = 0V | 3 |
| Zero Gate Voltage Drain Current (Q2 P-Channel) | IDSS |  |  | -1 | µA | VDS = -20V, VGS = 0V | 3 |
| Static Drain-Source On-Resistance (Q2 P-Channel) | RDS(ON) |  |  | 74 | mΩ | VGS = -4.5V, ID = -3.5A | 3 |
| Static Drain-Source On-Resistance (Q2 P-Channel) | RDS(ON) |  |  | 110 | mΩ | VGS = -2.5V, ID = -3.0A | 3 |
| Static Drain-Source On-Resistance (Q2 P-Channel) | RDS(ON) |  |  | 168 | mΩ | VGS = -1.8V, ID = -2.0A | 3 |
| Diode Forward Voltage (Q2 P-Channel) | VSD |  | -0.8 | -1.2 | V | VGS = 0V, IS = -1A | 3 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | tin |  Terminals Connections: See Diagram  Terminals: Finish, Matte Tin Annealed over Copper Leadframe. | 1 |

## CAD (KiCad official)

- Symbol: `DMC2053UVT-7`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-6`
- 3D model: TSOT-26 (KiCad packages3D, STEP)
- 3D model files: `dmc2053uvt-7-etched.step` / `dmc2053uvt-7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmc2053uvt-7.step` / `dmc2053uvt-7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885265544437760) (10 pp, sha256 `7c137ad91e456e0c`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dmc2053uvt-7-datasheet.pdf)