DM9161EP

{
  "slug": "dm9161ep",
  "version": "0.1.0",
  "type": "component",
  "description": "DAVICOM Ethernet Transceivers, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "dm9161ep",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "dm9161ep.kicad_sym",
    "dm9161ep.kicad_mod",
    "dm9161ep.glb",
    "dm9161ep.step",
    "dm9161ep.lbr",
    "docs/hero.png",
    "docs/dm9161ep-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "dm9161ep-hero.glb",
    "dm9161ep-hero.overlay.json",
    "dm9161ep-etched.glb"
  ],
  "component": {
    "mpn": "DM9161EP",
    "manufacturer": "DAVICOM",
    "package": "LQFP-48(7x7)",
    "pin_count": 48,
    "category": "Interface",
    "subcategory": "Ethernet Transceivers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893089959829504",
    "parts": {
      "symbol": "dm9161ep.kicad_sym",
      "footprint": "dm9161ep.kicad_mod",
      "model_3d": "dm9161ep-hero.glb",
      "model_3d_plain": "dm9161ep-etched.glb",
      "model_3d_step": "dm9161ep-etched.step",
      "model_3d_step_plain": "dm9161ep.step",
      "lbr": "dm9161ep.lbr"
    },
    "distributor_links": {
      "lcsc": "C965908"
    },
    "distributor_check": {
      "checked_at": "2026-10-19T05:10:45Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog receive power supply pin; the datasheet specifies a single low-power 3.3V supply."
      },
      {
        "number": "2",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog receive power supply pin, connected to the same analog receive supply as pin 1."
      },
      {
        "number": "3",
        "name": "RX+/FXRD+",
        "type": "input",
        "description": "Positive leg of the differential receive pair from the media; carries pseudo-ECL signal in fiber mode."
      },
      {
        "number": "4",
        "name": "RX-/FXRD-",
        "type": "input",
        "description": "Negative leg of the differential receive pair from the media; carries pseudo-ECL signal in fiber mode."
      },
      {
        "number": "5",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog receive ground."
      },
      {
        "number": "6",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog transmit ground."
      },
      {
        "number": "7",
        "name": "TX+/FXTD+",
        "type": "output",
        "description": "Positive leg of the differential transmit pair to the media; transmits pseudo-ECL signal in fiber mode."
      },
      {
        "number": "8",
        "name": "TX-/FXTD-",
        "type": "output",
        "description": "Negative leg of the differential transmit pair to the media; transmits pseudo-ECL signal in fiber mode."
      },
      {
        "number": "9",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog transmit power supply pin."
      },
      {
        "number": "10",
        "name": "PWRDWN",
        "type": "input",
        "description": "Asserted high to force power-down mode, leaving only the MDC/MDIO management logic active; the device leaves power-down only after hardware or software reset with PWRDWN low."
      },
      {
        "number": "11",
        "name": "FDX/COLLED#/OP0",
        "type": "output",
        "description": "Full-duplex LED output (or full-duplex/collision LED when register 16 bit 5 is set), and OP0 power-up/reset latch input that selects the forced or advertised operating mode per Table A."
      },
      {
        "number": "12",
        "name": "SPEEDLED#/OP1",
        "type": "output",
        "description": "Speed LED output, active to indicate 100 Mbps mode, and OP1 power-up/reset latch input that selects the operating mode per Table A."
      },
      {
        "number": "13",
        "name": "LINK/ACTLED#/OP2",
        "type": "output",
        "description": "Link and activity LED output for 10 and 100 Mbps operation, and OP2 power-up/reset latch input that selects the operating mode per Table A."
      },
      {
        "number": "14",
        "name": "CABLESTS/LINKSTS",
        "type": "output",
        "description": "Cable status output when latched low at power-up (default) or link status output when latched high."
      },
      {
        "number": "15",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground."
      },
      {
        "number": "16",
        "name": "TXER/TXD[4]",
        "type": "input",
        "description": "Transmit error input in 100 Mbps mode (substitutes HALT when TXEN is active and ignored at 10 Mbps); becomes the fifth TXD data bit TXD[4] in bypass 4B5B mode."
      },
      {
        "number": "17",
        "name": "TXD[3]",
        "type": "input",
        "description": "MII transmit data bit 3, sampled synchronous to TXCLK in 10/100 Mbps nibble mode and ignored in 10 Mbps GPSI mode."
      },
      {
        "number": "18",
        "name": "TXD[2]",
        "type": "input",
        "description": "MII transmit data bit 2, sampled synchronous to TXCLK in 10/100 Mbps nibble mode and ignored in 10 Mbps GPSI mode."
      },
      {
        "number": "19",
        "name": "TXD[1]",
        "type": "input",
        "description": "MII transmit data bit 1, sampled synchronous to TXCLK in 10/100 Mbps nibble mode and ignored in 10 Mbps GPSI mode."
      },
      {
        "number": "20",
        "name": "TXD[0]",
        "type": "input",
        "description": "MII transmit data bit 0, synchronous to TXCLK; serves as the serial data input in 10 Mbps GPSI (7-wired) mode."
      },
      {
        "number": "21",
        "name": "TXEN",
        "type": "input",
        "description": "Transmit enable; active high indicates valid nibble data on TXD[0:3] (or valid 10 Mbps data on TXD[0] in GPSI mode)."
      },
      {
        "number": "22",
        "name": "TXCLK/ISOLATE",
        "type": "tri_state",
        "description": "Transmit clock output from the PHY (25 MHz in 100 Mbps nibble mode, 2.5 MHz in 10 Mbps nibble mode, 10 MHz in 10 Mbps GPSI mode); ISOLATE power-up latch sets register 0.10 to 0 or 1."
      },
      {
        "number": "23",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital power supply pin."
      },
      {
        "number": "24",
        "name": "MDC",
        "type": "input",
        "description": "Management Data Clock input from the station management entity, up to 2.5 MHz."
      },
      {
        "number": "25",
        "name": "MDIO",
        "type": "bidirectional",
        "description": "Bidirectional management data I/O, which may be driven by the station management entity or by the PHY."
      },
      {
        "number": "26",
        "name": "RXD[3]/PHYAD[3]",
        "type": "tri_state",
        "description": "MII receive data bit 3 output, synchronous to RXCLK in 10/100 Mbps MII mode; also the PHY address bit 3 power-up/reset latch input."
      },
      {
        "number": "27",
        "name": "RXD[2]/PHYAD[2]",
        "type": "tri_state",
        "description": "MII receive data bit 2 output, synchronous to RXCLK in 10/100 Mbps MII mode; also the PHY address bit 2 power-up/reset latch input."
      },
      {
        "number": "28",
        "name": "RXD[1]/PHYAD[1]",
        "type": "tri_state",
        "description": "MII receive data bit 1 output, synchronous to RXCLK in 10/100 Mbps MII mode; also the PHY address bit 1 power-up/reset latch input."
      },
      {
        "number": "29",
        "name": "RXD[0]/PHYAD[0]",
        "type": "tri_state",
        "description": "MII receive data bit 0 output, synchronous to RXCLK; serves as the serial data output in 10 Mbps GPSI mode, and is also the PHY address bit 0 power-up/reset latch input."
      },
      {
        "number": "30",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital power supply pin."
      },
      {
        "number": "31",
        "name": "RXEN",
        "type": "input",
        "description": "Active high enables RXD[0:3], RXCLK, and RXDV outputs; active low tri-states these outputs; pull high in node applications."
      },
      {
        "number": "32",
        "name": "MDINTR#",
        "type": "output",
        "description": "Active-low status interrupt output asserted on any link, speed, or duplex change; it is high-impedance and requires a 2.2 kΩ pull-up resistor."
      },
      {
        "number": "33",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground."
      },
      {
        "number": "34",
        "name": "RXCLK/SCRAMEN/10BTSER",
        "type": "tri_state",
        "description": "Receive clock output from the PHY (25 MHz in 100 Mbps MII, 2.5 MHz in 10 Mbps MII, 10 MHz in 10 Mbps GPSI); power-up latch selects scrambler enable or 10 Mbps serial mode, and is only supported in forced 100M or 10M modes."
      },
      {
        "number": "35",
        "name": "CRS/PHYAD[4]",
        "type": "tri_state",
        "description": "Carrier sense output asserted high for carrier due to receive or transmit activity in half-duplex mode (receive only in full-duplex or repeater mode); also the PHY address bit 4 power-up/reset latch input."
      },
      {
        "number": "36",
        "name": "COL/RMII",
        "type": "tri_state",
        "description": "Collision detect output asserted high in 10/100 Mbps half-duplex mode (always low in full-duplex); power-up latch selects Reduced MII when high (default low for Normal MII)."
      },
      {
        "number": "37",
        "name": "RXDV/TESTMODE",
        "type": "tri_state",
        "description": "Receive data valid output asserted high when valid data is presented on RXD[0:3]; power-up latch enables test mode when high (default 0, normal operation)."
      },
      {
        "number": "38",
        "name": "RXER/RXD[4]/RPTR",
        "type": "tri_state",
        "description": "Receive error output asserted high on invalid symbol detection; becomes RXD[4] in decoder bypass mode; power-up latch selects Repeater mode when high or Node mode when low (default)."
      },
      {
        "number": "39",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital power supply pin."
      },
      {
        "number": "40",
        "name": "RESET#",
        "type": "input",
        "description": "Active-low input that initializes the DM9161 when asserted."
      },
      {
        "number": "41",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital power supply pin."
      },
      {
        "number": "42",
        "name": "XT2",
        "type": "bidirectional",
        "description": "Crystal output (25 MHz crystal in normal MII mode); serves as the REF_CLK input (50 MHz) in RMII mode."
      },
      {
        "number": "43",
        "name": "XT1",
        "type": "input",
        "description": "Crystal input (25 MHz crystal in normal MII and GPSI modes; floating in RMII mode)."
      },
      {
        "number": "44",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground."
      },
      {
        "number": "45",
        "name": "SD",
        "type": "input",
        "description": "Fiber-optic PECL signal detect input, indicating whether the fiber receive pair is receiving valid signal levels."
      },
      {
        "number": "46",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog substrate ground."
      },
      {
        "number": "47",
        "name": "BGRESG",
        "type": "power_in",
        "description": "Bandgap ground."
      },
      {
        "number": "48",
        "name": "BGRES",
        "type": "output",
        "description": "Bandgap voltage reference resistor connection; a 6.8 kΩ resistor is used here."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Multi-function pins with power-up/reset latch functions. The type shown is the datasheet's output (O; Pins 3/4/7/8 and 45 are fiber-mode (FX) alternate functions; the table lists them as TP/FX shared pi; The MPN DM9161EP was not matched to a package in the provided text. The Order Information section (p"
        ],
        "pages_sent": 17,
        "cost_usd": 0.115,
        "at": "2026-10-19T05:10:25"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893089959829504",
        "pages": 50,
        "sha256": "0126968b71ebf164",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 48,
        "described": 48,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "dm9161ep.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          9.0,
          9.0,
          1.5
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "9dea352d93177c2904afd7d7b68ea8855ce1ab691f69f8b3e13655600514b6bf",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "dm9161ep-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          1.5
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "e29fa39d5515cc4203924b43be50f278a65180315f242c56d9ff492b29d18196",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}