DM9161AEP

{
  "schema_version": 1,
  "type": "component",
  "slug": "dm9161aep",
  "title": "DM9161AEP",
  "brief": "DAVICOM Ethernet Controllers, LQFP-48(7x7). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "interface",
    "dm9161aep"
  ],
  "component": {
    "mpn": "DM9161AEP",
    "manufacturer": "DAVICOM",
    "package": "LQFP-48(7x7)",
    "pin_count": 48,
    "category": "Interface",
    "subcategory": "Ethernet Controllers",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/1f1c1f2e1b1449ef8ac52c5746bd6c64.pdf",
    "parts": {
      "symbol": "dm9161aep.kicad_sym",
      "footprint": "dm9161aep.kicad_mod",
      "model_3d": "dm9161aep-etched.glb",
      "model_3d_plain": "dm9161aep.glb",
      "model_3d_step": "dm9161aep-etched.step",
      "model_3d_step_plain": "dm9161aep.step",
      "lbr": "dm9161aep.lbr"
    },
    "distributor_links": {
      "lcsc": "C18215"
    },
    "pins": [
      {
        "number": "1",
        "name": "AVDDR",
        "type": "power_in",
        "description": "Analog receive supply, +3.3V nominal. Decouple locally with 100nF and a ferrite/pi-filter from the main analog rail."
      },
      {
        "number": "2",
        "name": "AVDDR",
        "type": "power_in",
        "description": "Analog receive supply, +3.3V nominal (second pin of the AVDDR net). Decouple locally with 100nF."
      },
      {
        "number": "3",
        "name": "RX+",
        "type": "input",
        "description": "Differential receive pair positive input from the magnetics/RJ45 (100Ω differential). Carries data recovered from the media."
      },
      {
        "number": "4",
        "name": "RX-",
        "type": "input",
        "description": "Differential receive pair negative input from the magnetics/RJ45 (100Ω differential)."
      },
      {
        "number": "5",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog receive ground. Tie to the analog ground plane."
      },
      {
        "number": "6",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog transmit ground. Tie to the analog ground plane."
      },
      {
        "number": "7",
        "name": "TX+",
        "type": "output",
        "description": "Differential transmit pair positive output to the magnetics (100BASE-TX MLT-3 or 10BASE-T Manchester). Drives 1:1 or 1.25:1 transformer."
      },
      {
        "number": "8",
        "name": "TX-",
        "type": "output",
        "description": "Differential transmit pair negative output to the magnetics."
      },
      {
        "number": "9",
        "name": "AVDDT",
        "type": "power_in",
        "description": "Analog transmit supply, +3.3V nominal. Decouple locally with 100nF and a ferrite from the analog rail."
      },
      {
        "number": "10",
        "name": "PWRDWN",
        "type": "input",
        "description": "Power-down control (active high). When high, most blocks power off; only MDC/MDIO management remains active. A hardware or software reset with PWRDWN low is required to exit power-down."
      },
      {
        "number": "11",
        "name": "LED0/OP0",
        "type": "bidirectional",
        "description": "LED driver output 0 (post-reset). During power-up/reset it is latched as OP0, one of the mode-select strap bits per Table A (media type selection). Weak internal pull-up."
      },
      {
        "number": "12",
        "name": "LED1/OP1",
        "type": "bidirectional",
        "description": "LED driver output 1 (post-reset). Latched as OP1 mode-select strap at reset per Table A. Weak internal pull-up."
      },
      {
        "number": "13",
        "name": "LED2/OP2",
        "type": "bidirectional",
        "description": "LED driver output 2 (post-reset). Latched as OP2 mode-select strap at reset per Table A. Weak internal pull-up."
      },
      {
        "number": "14",
        "name": "CABLESTS/LINKSTS",
        "type": "bidirectional",
        "description": "Cable-status or link-status output. Function selected by the reset latch state: latch low = cable-status (1 = cable present), latch high = link-status (0 = link up). Weak internal pull-down."
      },
      {
        "number": "15",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground. Tie to the digital ground plane."
      },
      {
        "number": "16",
        "name": "TXER/TXD[4]",
        "type": "input",
        "description": "Transmit Error in 100BASE-TX MII mode (active high injects HALT symbol). Ignored in 10Mbps. In 4B/5B bypass mode this pin carries the 5th TXD[4] data bit."
      },
      {
        "number": "17",
        "name": "TXD[3]",
        "type": "input",
        "description": "MII transmit data bit 3, synchronous to TXCLK in 10/100Mbps nibble mode. Ignored in 10Mbps GPSI 7-wired mode."
      },
      {
        "number": "18",
        "name": "TXD[2]",
        "type": "input",
        "description": "MII transmit data bit 2, synchronous to TXCLK in 10/100Mbps nibble mode. Ignored in 10Mbps GPSI 7-wired mode."
      },
      {
        "number": "19",
        "name": "TXD[1]",
        "type": "input",
        "description": "MII transmit data bit 1, synchronous to TXCLK in 10/100Mbps nibble mode. Ignored in 10Mbps GPSI 7-wired mode."
      },
      {
        "number": "20",
        "name": "TXD[0]",
        "type": "input",
        "description": "MII transmit data bit 0, synchronous to TXCLK in 10/100Mbps nibble mode. Serves as the serial transmit data input in 10Mbps GPSI 7-wired mode."
      },
      {
        "number": "21",
        "name": "TXEN",
        "type": "input",
        "description": "Transmit Enable (active high). Indicates valid nibble data on TXD[3:0] in 100Mbps and 10Mbps nibble modes, or valid serial data on TXD[0] in 10Mbps GPSI 7-wired mode."
      },
      {
        "number": "22",
        "name": "TXCLK/ISOLATE",
        "type": "tri_state",
        "description": "Transmit clock output from the PHY: 25MHz in 100Mbps MII, 2.5MHz in 10Mbps MII, 10MHz in 10Mbps GPSI. Also latched at reset as ISOLATE (0 = normal, 1 = MII isolate, Reg 0.10 = 1). Weak internal pull-down at reset."
      },
      {
        "number": "23",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital I/O supply, +3.3V nominal (5V tolerant I/Os). Decouple locally with 100nF."
      },
      {
        "number": "24",
        "name": "MDC",
        "type": "input",
        "description": "Management data clock provided by the MAC/STA, up to 12.5MHz. Clocks the MDIO serial management interface."
      },
      {
        "number": "25",
        "name": "MDIO",
        "type": "bidirectional",
        "description": "Management data I/O, bidirectional serial data for accessing PHY MII registers. Requires an external ~1.5kΩ pull-up."
      },
      {
        "number": "26",
        "name": "RXD[3]/PHYAD[3]",
        "type": "tri_state",
        "description": "MII receive data bit 3, synchronous to RXCLK. Also latched at power-up/reset as PHYAD[3], part of the PHY address strap. Weak internal pull-down at reset."
      },
      {
        "number": "27",
        "name": "RXD[2]/PHYAD[2]",
        "type": "tri_state",
        "description": "MII receive data bit 2, synchronous to RXCLK. Latched at reset as PHYAD[2]. Weak internal pull-down at reset."
      },
      {
        "number": "28",
        "name": "RXD[1]/PHYAD[1]",
        "type": "tri_state",
        "description": "MII receive data bit 1, synchronous to RXCLK. Latched at reset as PHYAD[1]. Weak internal pull-down at reset."
      },
      {
        "number": "29",
        "name": "RXD[0]/PHYAD[0]",
        "type": "tri_state",
        "description": "MII receive data bit 0, synchronous to RXCLK. In 10Mbps GPSI 7-wired mode this pin is the serial data output. Latched at reset as PHYAD[0]. Weak internal pull-down at reset."
      },
      {
        "number": "30",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital I/O supply, +3.3V nominal. Decouple locally with 100nF."
      },
      {
        "number": "31",
        "name": "LEDMODE",
        "type": "input",
        "description": "LED mode select input. 0 = dual-LED mode, 1 = normal LED mode; picks how LED0..LED3 encode link/activity/speed/duplex."
      },
      {
        "number": "32",
        "name": "MDINTR#",
        "type": "tri_state",
        "description": "Status interrupt output. Asserted on link/speed/duplex change per interrupt register 21. Active polarity is programmable (asserts low when pulled up, high when pulled down). Weak internal pull-down at reset."
      },
      {
        "number": "33",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground."
      },
      {
        "number": "34",
        "name": "RXCLK/10BTSER",
        "type": "tri_state",
        "description": "Receive clock output from the PHY: 25MHz in 100Mbps MII, 2.5MHz in 10Mbps MII, 10MHz in 10Mbps GPSI. Latched at reset as 10BTSER (0 = 10Mbps GPSI, 1 = 10Mbps MII). Weak internal pull-up at reset."
      },
      {
        "number": "35",
        "name": "CRS/PHYAD[4]",
        "type": "tri_state",
        "description": "Carrier-Sense output (active high) indicating TX or RX activity in half-duplex; in full-duplex/repeater asserts only for RX activity. Latched at reset as PHYAD[4], the top PHY-address bit. Weak internal pull-down at reset."
      },
      {
        "number": "36",
        "name": "COL/RMII",
        "type": "tri_state",
        "description": "Collision detection output (asserted high in 10/100Mbps half-duplex; always 0 in full-duplex). Latched at reset as RMII enable: 0 = Normal MII, 1 = Reduced MII. Weak internal pull-down."
      },
      {
        "number": "37",
        "name": "RXDV/TESTMODE",
        "type": "tri_state",
        "description": "Receive Data Valid, asserted high while RXD[3:0] carries valid data. Latched at reset as TESTMODE (0 = normal, 1 = test mode). Weak internal pull-down at reset."
      },
      {
        "number": "38",
        "name": "RXER/RXD[4]/RPTR",
        "type": "tri_state",
        "description": "Receive Error output in MII mode; asserted on invalid symbol. In 4B/5B decoder-bypass mode becomes RXD[4]. Latched at reset as RPTR: 0 = Node mode, 1 = Repeater mode. Weak internal pull-down at reset."
      },
      {
        "number": "39",
        "name": "DISMDIX",
        "type": "input",
        "description": "HP Auto-MDIX control input. 0 = enable Auto-MDIX crossover detection, 1 = disable Auto-MDIX (fixed MDI). Weak internal pull-down."
      },
      {
        "number": "40",
        "name": "RESET#",
        "type": "input",
        "description": "Active-low hardware reset input. Holds the DM9161A in reset while low; releases to initialize registers and latch reset-strap inputs."
      },
      {
        "number": "41",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital I/O supply, +3.3V nominal."
      },
      {
        "number": "42",
        "name": "XT2",
        "type": "bidirectional",
        "description": "25MHz crystal output; also serves as the 50MHz REF_CLK single-ended input when the PHY is used in RMII mode."
      },
      {
        "number": "43",
        "name": "XT1",
        "type": "input",
        "description": "25MHz crystal input (XT1-XT2 across a parallel-resonant crystal with load capacitors)."
      },
      {
        "number": "44",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground."
      },
      {
        "number": "45",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect. Leave floating or tie to ground per Davicom reference design."
      },
      {
        "number": "46",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog substrate ground. Tie to the analog ground plane."
      },
      {
        "number": "47",
        "name": "BGRESG",
        "type": "passive",
        "description": "Bandgap reference resistor ground return. Connects one end of the external 6.8kΩ ±1% bandgap reference resistor to analog ground."
      },
      {
        "number": "48",
        "name": "BGRES",
        "type": "passive",
        "description": "Bandgap voltage reference. Tie an external 6.8kΩ ±1% resistor between BGRES and BGRESG to set the internal bias current."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/1f1c1f2e1b1449ef8ac52c5746bd6c64.pdf",
        "pages": 45,
        "sha256": "166788920e65d687",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 48,
        "described": 48,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -4.1625,
        -2.75
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "LQFP-48_7x7mm_P0.5mm@sha256:1ccc5ad4d95398a4",
      "mark": "drawn"
    },
    "models_3d": [
      {
        "file": "dm9161aep.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          9,
          9,
          1.5
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "9dea352d93177c2904afd7d7b68ea8855ce1ab691f69f8b3e13655600514b6bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "dm9161aep-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          9,
          9,
          1.5
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "299d46637761c61c0d73c5137dcd24536df75c8a9e889535ae48cc5491722d69",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "DAVICOM",
      "Package": "LQFP-48(7x7)",
      "Category": "Interface",
      "Pins": "48"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "dm9161aep"
  ],
  "discovery_pitch": "DM9161AEP (DAVICOM) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "dm9161aep.kicad_sym",
    "dm9161aep.kicad_mod",
    "dm9161aep.glb",
    "dm9161aep.step",
    "dm9161aep-etched.step",
    "dm9161aep.lbr",
    "docs/hero.png",
    "docs/dm9161aep-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "DM9161AEP",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-24T19:48:38.076Z"
}