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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DM9051NP

DAVICOM · Ethernet Controllers · QFN-32-EP(5x5)

DM9051NP from DAVICOM, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BGRES	passive	Bandgap reference resistor pin; the datasheet pin drawing gives no further detail.
2	VDD18	power_in	1.8V supply pin for core and analog blocks, fed from the integrated 3.3V to 1.8V regulator.
3	RX+	input	Positive differential receive input of the integrated 10/100M transceiver.
4	RX-	input	Negative differential receive input of the integrated 10/100M transceiver.
5	GND	power_in	Ground pin.
6	TX+	output	Positive differential transmit output of the integrated 10/100M transceiver.
7	TX-	output	Negative differential transmit output of the integrated 10/100M transceiver.
8	VDD18	power_in	1.8V supply pin for core and analog blocks, fed from the integrated 3.3V to 1.8V regulator.
9	TEST3	input	Test pin 3; the datasheet pin drawing gives no further detail.
10	GP1	bidirectional	General purpose I/O pin 1, 5V/3.3V tolerant.
11	EEDIO	bidirectional	EEPROM data input/output pin for the EEPROM interface.
12	EECK	output	EEPROM clock output for the EEPROM interface.
13	EECS	output	EEPROM chip select output for the EEPROM interface.
14	WOL	output	Wake-up on LAN signal output.
15	VCC33	power_in	3.3V supply pin.
16	FDXLED	output	Full-duplex status LED output.
17	SPI_CSN	input	SPI chip select input, active low, 5V/3.3V tolerant.
18	SPI_CK	input	SPI clock input with clock speeds up to 50MHz/160MHz.
19	SPI_MOSI	input	SPI data input from the host (master out, slave in).
20	SPI_MISO	output	SPI data output to the host (master in, slave out).
21	VCC33	power_in	3.3V supply pin.
22	TEST2	input	Test pin 2; the datasheet pin drawing gives no further detail.
23	GP2	bidirectional	General purpose I/O pin 2, 5V/3.3V tolerant.
24	IRQ	output	Interrupt request output to the host processor.
25	LINKLED	output	Link status LED output.
26	SPDLED	output	Speed status LED output.
27	RSTB	input	Active-low reset input.
28	GP3	bidirectional	General purpose I/O pin 3, 5V/3.3V tolerant.
29	VCC33	power_in	3.3V supply pin.
30	X2	output	Crystal oscillator output pin.
31	X1	input	Crystal oscillator input pin.
32	GND	power_in	Ground pin.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	DAVICOM
Package	QFN-32-EP(5x5)
Category	Interface
Pins	33

CAD (KiCad official)

Symbol: DM9051NP
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: dm9051np-etched.step / dm9051np-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dm9051np.step / dm9051np.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: DAVICOM datasheet (4 pp, sha256 af5a20943b0e33fd, retrieved 2026-10-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF