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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

DM9000CIEP

DAVICOM · Ethernet ICs · LQFP-48(7x7)

DM9000CIEP from DAVICOM, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BGRES	bidirectional	Band gap pin; the datasheet states no further function or limit for it.
2	RXVDD18	power_out	1.8V power output for the twisted-pair receive circuitry, supplied by the internal 3.3V-to-1.8V regulator.
3	RX+	bidirectional	Twisted-pair receive pin, acting as the receive input in MDI mode or the transmit output in MDIX mode.
4	RX-	bidirectional	Twisted-pair receive pin, acting as the receive input in MDI mode or the transmit output in MDIX mode.
5	RXGND	power_in	Ground for the twisted-pair receive circuitry.
6	TXGND	power_in	Ground for the twisted-pair transmit circuitry.
7	TX+	bidirectional	Twisted-pair transmit pin, acting as the transmit output in MDI mode or the receive input in MDIX mode.
8	TX-	bidirectional	Twisted-pair transmit pin, acting as the transmit output in MDI mode or the receive input in MDIX mode.
9	TXVDD18	power_out	1.8V power output for the twisted-pair transmit circuitry, supplied by the internal regulator.
10	SD7	bidirectional	Processor data bus bit 7 in 16-bit and 8-bit modes; internal pull-low of about 60K.
11	SD6	bidirectional	Processor data bus bit 6; internal pull-low of about 60K.
12	SD5	bidirectional	Processor data bus bit 5; internal pull-low of about 60K.
13	SD4	bidirectional	Processor data bus bit 4; internal pull-low of about 60K.
14	SD3	bidirectional	Processor data bus bit 3; internal pull-low of about 60K.
15	GND	power_in	Digital ground.
16	SD2	bidirectional	Processor data bus bit 2; internal pull-low of about 60K.
17	SD1	bidirectional	Processor data bus bit 1; internal pull-low of about 60K.
18	SD0	bidirectional	Processor data bus bit 0; internal pull-low of about 60K.
19	EEDIO	bidirectional	Data input/output to and from the EEPROM.
20	EECK	output	Clock output to the EEPROM; this pin is also the strap that sets INT polarity (pulled high gives INT active low).
21	EECS	output	Chip-select output to the EEPROM; this pin is also the strap that sets the memory data bus width (pulled high gives 8-bit, otherwise 16-bit).
22	SD15	bidirectional	Processor data bus bit 15 in 16-bit mode; in 8-bit mode this pin is WAKE (wake-up signal output and CS# polarity strap).
23	VDD	power_in	Digital 3.3V power input.
24	SD14	bidirectional	Processor data bus bit 14 in 16-bit mode; in 8-bit mode this pin is LED3 (full-duplex LED output).
25	SD13	bidirectional	Processor data bus bit 13 in 16-bit mode; in 8-bit mode this pin is GP6 (general-purpose output and INT output-type strap).
26	SD12	bidirectional	Processor data bus bit 12 in 16-bit mode; in 8-bit mode this pin is GP5 (general-purpose output).
27	SD11	bidirectional	Processor data bus bit 11 in 16-bit mode; in 8-bit mode this pin is GP4 (general-purpose output).
28	SD10	bidirectional	Processor data bus bit 10 in 16-bit mode; in 8-bit mode this pin is GP3 (general-purpose I/O, input at default).
29	SD9	bidirectional	Processor data bus bit 9 in 16-bit mode; in 8-bit mode this pin is GP2 (general-purpose I/O, input at default).
30	VDD	power_in	Digital 3.3V power input.
31	SD8	bidirectional	Processor data bus bit 8 in 16-bit mode; in 8-bit mode this pin is GP1 (general-purpose I/O, input at default).
32	CMD	input	Command type select: high selects the DATA port access, low selects the INDEX port access.
33	GND	power_in	Digital ground.
34	INT	output	Interrupt request output, high active by default and low active when set by the EEPROM or the EECK strap.
35	IOR#	input	Processor read command, low active by default with polarity modifiable through EEPROM setting.
36	IOW#	input	Processor write command, low active by default with polarity modifiable through EEPROM setting.
37	CS#	input	Chip select, low active by default to select the DM9000C/CI, with polarity modifiable through EEPROM setting.
38	LED2	bidirectional	Link/Active LED; in LED mode 1 it combines link and carrier sense, in LED mode 0 it shows carrier sense only, and it is disabled when this pin is used for WOL.
39	LED1	bidirectional	Speed LED; low output indicates 100M/S operation, and the pin floats for 10M operation.
40	PWRST#	input	Active-low power-on reset; the device is ready 5us after this pin is deasserted.
41	TEST	input	Operation mode pin that must be forced to ground in normal application.
42	VDD	power_in	Digital 3.3V power input.
43	X2	output	25MHz crystal output.
44	X1	input	25MHz crystal input.
45	GND	power_in	Digital ground.
46	SD	input	Fiber-optic signal detect, PECL level, indicating whether the fiber receive pair is receiving valid levels.
47	RXGND	power_in	Ground for the twisted-pair receive circuitry.
48	BGGND	power_in	Band gap ground.

Key specifications

Parameter	Value
Manufacturer	DAVICOM
Package	LQFP-48(7x7)
Category	Interface ICs
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (absolute maximum)	DVDD	-0.3		3.6	V		51
DC Input Voltage (absolute maximum)	VIN	-0.5		5.5	V		51
DC Output Voltage (absolute maximum)	VOUT	-0.3		3.6	V		51
Storage Temperature range	Tstg	-65		150	℃		51
Ambient Temperature (industrial)	TA	-40		85	°C	For DM9000CIEP	51
Lead Temperature (soldering)	LT			260	℃	TL, soldering, 10 sec.	51
Supply Voltage (operating)	DVDD	3.135	3.3	3.465	V		51
Input High Voltage	VIH	2			V		52
Input Low Leakage Current	IIL	-1			uA	VIN = 0.0V	52
Input High Leakage Current	IIH			1	uA	VIN = 3.3V	52
100TX+/- Differential Rise/Fall Time	tTR/F	3		5	ns		52
100TX+/- Differential Rise/Fall Time Mismatch	tTM	0		0.5	ns		52
100TX+/- Differential Output Duty Cycle Distortion	tTDC	0		0.5	ns		52
100TX+/- Differential Output Peak-to-Peak Jitter	Tt/T	0		1.4	ns		52
100TX+/- Differential Voltage Overshoot	XOST	0		5	%		52
OSC Clock Cycle	TCKC	39.9988	40	40.0012	ns	30ppm	52
OSC Pulse Width High	TPWH	16	20	24	ns		52
OSC Pulse Width Low	TPWL	16	20	24	ns		52
PWRST# Low Period	T1	1			ms		52
Strap pin hold time with PWRST#	T2	40			ns		52
PWRST# high to EECS burst end	T4			3	ms		52
PWRST# high to EECS high	T3		11.31		us		52
Supply current, 100BASE-TX			130		mA	3.3V	51
Supply current, 10BASE-T TX			170		mA	3.3V	51
Supply current, 10BASE-T TX (100% utilization)			160		mA	3.3V, power saving	51
Supply current, 10BASE-T idle			60		mA	3.3V, power saving	51
Supply current, Auto-negotiation			60		mA	3.3V	51
Supply current, Power Down Mode			20		mA	3.3V	51
Supply current, Power Down Mode (system clock off)			6		mA	3.3V	51

CAD (KiCad official)

Symbol: DM9000CIEP
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: dm9000ciep-etched.step / dm9000ciep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dm9000ciep.step / dm9000ciep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: DAVICOM datasheet (63 pp, sha256 fc082ed410a7a3ec, retrieved 2026-10-25, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF