component
DM9000CEP
Public Made by Adomby adom
DAVICOM Ethernet Controllers, LQFP-48(7x7). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+366−8@@ -1,13 +1,376 @@ {+ "schema_version": 1,+ "type": "component", "slug": "dm9000cep",+ "title": "DM9000CEP",+ "brief": "DAVICOM Ethernet Controllers, LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "DAVICOM Ethernet Controllers, LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "interface", "dm9000cep" ],+ "component": {+ "mpn": "DM9000CEP",+ "manufacturer": "DAVICOM",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Interface",+ "subcategory": "Ethernet Controllers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586183869435822080",+ "parts": {+ "symbol": "dm9000cep.kicad_sym",+ "footprint": "dm9000cep.kicad_mod",+ "model_3d": "dm9000cep.glb",+ "model_3d_step": "dm9000cep.step",+ "lbr": "dm9000cep.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "BGRES",+ "type": "passive",+ "description": "Band-gap reference pin; connect an external precision resistor to set the internal band-gap current bias."+ },+ {+ "number": "2",+ "name": "RXVDD18",+ "type": "power_out",+ "description": "1.8 V regulator output for the TP receive analog block. Decouple locally; do not drive from an external supply."+ },+ {+ "number": "3",+ "name": "RX+",+ "type": "bidirectional",+ "description": "10/100BASE-T twisted-pair receive positive in MDI mode, or transmit positive in MDIX mode."+ },+ {+ "number": "4",+ "name": "RX-",+ "type": "bidirectional",+ "description": "10/100BASE-T twisted-pair receive negative in MDI mode, or transmit negative in MDIX mode."+ },+ {+ "number": "5",+ "name": "RXGND",+ "type": "power_in",+ "description": "Analog ground for the RX/receive PHY block."+ },+ {+ "number": "6",+ "name": "TXGND",+ "type": "power_in",+ "description": "Analog ground for the TX/transmit PHY block."+ },+ {+ "number": "7",+ "name": "TX+",+ "type": "bidirectional",+ "description": "10/100BASE-T twisted-pair transmit positive in MDI mode, or receive positive in MDIX mode."+ },+ {+ "number": "8",+ "name": "TX-",+ "type": "bidirectional",+ "description": "10/100BASE-T twisted-pair transmit negative in MDI mode, or receive negative in MDIX mode."+ },+ {+ "number": "9",+ "name": "TXVDD18",+ "type": "power_out",+ "description": "1.8 V regulator output for the TP transmit analog block. Decouple locally; do not drive externally."+ },+ {+ "number": "10",+ "name": "SD7",+ "type": "bidirectional",+ "description": "Processor data bus bit 7 (host interface). Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "11",+ "name": "SD6",+ "type": "bidirectional",+ "description": "Processor data bus bit 6 (host interface). Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "12",+ "name": "SD5",+ "type": "bidirectional",+ "description": "Processor data bus bit 5 (host interface). Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "13",+ "name": "SD4",+ "type": "bidirectional",+ "description": "Processor data bus bit 4 (host interface). Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "14",+ "name": "SD3",+ "type": "bidirectional",+ "description": "Processor data bus bit 3 (host interface). Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "15",+ "name": "GND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "16",+ "name": "SD2",+ "type": "bidirectional",+ "description": "Processor data bus bit 2 (host interface). Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "17",+ "name": "SD1",+ "type": "bidirectional",+ "description": "Processor data bus bit 1 (host interface). Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "18",+ "name": "SD0",+ "type": "bidirectional",+ "description": "Processor data bus bit 0 (host interface). Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "19",+ "name": "EEDIO",+ "type": "bidirectional",+ "description": "Serial data I/O for the external 93C46-style EEPROM. Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "20",+ "name": "EECK",+ "type": "output",+ "description": "Serial clock to the external EEPROM. Also latched at power-on reset as a strap: pull-high \u2192 INT active-low, floating \u2192 INT active-high."+ },+ {+ "number": "21",+ "name": "EECS",+ "type": "output",+ "description": "Chip-select to the external EEPROM. Also latched at power-on reset as a strap: pull-high \u2192 8-bit host bus, floating \u2192 16-bit host bus."+ },+ {+ "number": "22",+ "name": "SD15/WAKE",+ "type": "bidirectional",+ "description": "16-bit mode: processor data bus bit 15. 8-bit mode: WAKE output - pulses on a wake-up event. Also latched at reset as a strap for CS# polarity in 8-bit mode (pull-high \u2192 CS# active-high, float \u2192 CS# active-low)."+ },+ {+ "number": "23",+ "name": "VDD",+ "type": "power_in",+ "description": "3.3 V digital supply input."+ },+ {+ "number": "24",+ "name": "SD14/LED3",+ "type": "bidirectional",+ "description": "16-bit mode: processor data bus bit 14. 8-bit mode: LED3 full-duplex LED output (open-drain low when internal PHY is full-duplex; LED mode is set in EEPROM)."+ },+ {+ "number": "25",+ "name": "SD13/GP6",+ "type": "bidirectional",+ "description": "16-bit mode: processor data bus bit 13. 8-bit mode: GP6 general-purpose output (register 1Fh); also acts at reset as a strap defining INT output type (pull-high \u2192 open-drain, float \u2192 force/push-pull)."+ },+ {+ "number": "26",+ "name": "SD12/GP5",+ "type": "bidirectional",+ "description": "16-bit mode: processor data bus bit 12. 8-bit mode: GP5 general-purpose output driven by register 1Fh."+ },+ {+ "number": "27",+ "name": "SD11/GP4",+ "type": "bidirectional",+ "description": "16-bit mode: processor data bus bit 11. 8-bit mode: GP4 general-purpose output driven by register 1Fh."+ },+ {+ "number": "28",+ "name": "SD10/GP3",+ "type": "bidirectional",+ "description": "16-bit mode: processor data bus bit 10. 8-bit mode: GP3 general-purpose I/O (registers GPCR/GPR); default is input."+ },+ {+ "number": "29",+ "name": "SD9/GP2",+ "type": "bidirectional",+ "description": "16-bit mode: processor data bus bit 9. 8-bit mode: GP2 general-purpose I/O (registers GPCR/GPR); default is input."+ },+ {+ "number": "30",+ "name": "VDD",+ "type": "power_in",+ "description": "3.3 V digital supply input."+ },+ {+ "number": "31",+ "name": "SD8/GP1",+ "type": "bidirectional",+ "description": "16-bit mode: processor data bus bit 8. 8-bit mode: GP1 general-purpose I/O (registers GPCR/GPR); default is input."+ },+ {+ "number": "32",+ "name": "CMD",+ "type": "input",+ "description": "Command type: high selects the DATA port for the current cycle, low selects the INDEX (address) port. Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "33",+ "name": "GND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "34",+ "name": "INT",+ "type": "output",+ "description": "Interrupt request to the host. High-active by default; polarity may be flipped by EEPROM setting or by the EECK strap. Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "35",+ "name": "IOR#",+ "type": "input",+ "description": "Processor read strobe. Low-active by default; polarity configurable via EEPROM. Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "36",+ "name": "IOW#",+ "type": "input",+ "description": "Processor write strobe. Low-active by default; polarity configurable via EEPROM. Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "37",+ "name": "CS#",+ "type": "input",+ "description": "Chip-select to the DM9000C/CI host interface. Low-active by default; polarity configurable via EEPROM (and by the WAKE strap in 8-bit mode). Internal pull-down ~60 k\u03a9."+ },+ {+ "number": "38",+ "name": "LED2",+ "type": "bidirectional",+ "description": "Link/Activity LED for the internal PHY (behavior depends on LED mode set in EEPROM word 7). Function is disabled when the pin is repurposed for the WOL output."+ },+ {+ "number": "39",+ "name": "LED1",+ "type": "bidirectional",+ "description": "Speed LED for the internal PHY: low drive indicates 100 Mb/s; floats in 10 Mb/s mode."+ },+ {+ "number": "40",+ "name": "PWRST#",+ "type": "input",+ "description": "Active-low power-on reset. The DM9000C/CI is ready ~5 \u00b5s after this pin is deasserted."+ },+ {+ "number": "41",+ "name": "TEST",+ "type": "input",+ "description": "Operation-mode/test pin. Tie to ground in normal application."+ },+ {+ "number": "42",+ "name": "VDD",+ "type": "power_in",+ "description": "3.3 V digital supply input."+ },+ {+ "number": "43",+ "name": "X2",+ "type": "output",+ "description": "25 MHz crystal oscillator output (connect to one leg of the crystal, or leave floating if X1 is driven by an external clock)."+ },+ {+ "number": "44",+ "name": "X1",+ "type": "input",+ "description": "25 MHz crystal oscillator input."+ },+ {+ "number": "45",+ "name": "GND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "46",+ "name": "SD",+ "type": "input",+ "description": "Fiber-optic Signal Detect (PECL input). Indicates whether the fiber-optic receive pair is receiving valid levels; tie appropriately when unused."+ },+ {+ "number": "47",+ "name": "RXGND",+ "type": "power_in",+ "description": "Analog ground for the RX/receive PHY block (second RXGND pin)."+ },+ {+ "number": "48",+ "name": "BGGND",+ "type": "power_in",+ "description": "Band-gap analog ground return."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586183869435822080",+ "pages": 63,+ "sha256": "ee55ca9f9a5216f5",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "DAVICOM",+ "Package": "LQFP-48(7x7)",+ "Category": "Interface",+ "Pins": "48"+ }+ },+ "variants": [+ {+ "mpn": "DM9000CEP",+ "kind": "packaging"+ },+ {+ "mpn": "DM9000CEPCIEP",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "dm9000cep"+ ],+ "discovery_pitch": "DM9000CEP (DAVICOM) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +388,5 @@ "docs/dm9000cep-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }