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DM9000CEP

Public Made by Adom

by adom

DAVICOM Ethernet Controllers, LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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DM9000CEP

DAVICOM · Ethernet Controllers · LQFP-48(7x7)

DM9000CEP from DAVICOM, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BGRES passive Band-gap reference pin; connect an external precision resistor to set the internal band-gap current bias.
2 RXVDD18 power_out 1.8 V regulator output for the TP receive analog block. Decouple locally; do not drive from an external supply.
3 RX+ bidirectional 10/100BASE-T twisted-pair receive positive in MDI mode, or transmit positive in MDIX mode.
4 RX- bidirectional 10/100BASE-T twisted-pair receive negative in MDI mode, or transmit negative in MDIX mode.
5 RXGND power_in Analog ground for the RX/receive PHY block.
6 TXGND power_in Analog ground for the TX/transmit PHY block.
7 TX+ bidirectional 10/100BASE-T twisted-pair transmit positive in MDI mode, or receive positive in MDIX mode.
8 TX- bidirectional 10/100BASE-T twisted-pair transmit negative in MDI mode, or receive negative in MDIX mode.
9 TXVDD18 power_out 1.8 V regulator output for the TP transmit analog block. Decouple locally; do not drive externally.
10 SD7 bidirectional Processor data bus bit 7 (host interface). Internal pull-down ~60 kΩ.
11 SD6 bidirectional Processor data bus bit 6 (host interface). Internal pull-down ~60 kΩ.
12 SD5 bidirectional Processor data bus bit 5 (host interface). Internal pull-down ~60 kΩ.
13 SD4 bidirectional Processor data bus bit 4 (host interface). Internal pull-down ~60 kΩ.
14 SD3 bidirectional Processor data bus bit 3 (host interface). Internal pull-down ~60 kΩ.
15 GND power_in Digital ground.
16 SD2 bidirectional Processor data bus bit 2 (host interface). Internal pull-down ~60 kΩ.
17 SD1 bidirectional Processor data bus bit 1 (host interface). Internal pull-down ~60 kΩ.
18 SD0 bidirectional Processor data bus bit 0 (host interface). Internal pull-down ~60 kΩ.
19 EEDIO bidirectional Serial data I/O for the external 93C46-style EEPROM. Internal pull-down ~60 kΩ.
20 EECK output Serial clock to the external EEPROM. Also latched at power-on reset as a strap: pull-high → INT active-low, floating → INT active-high.
21 EECS output Chip-select to the external EEPROM. Also latched at power-on reset as a strap: pull-high → 8-bit host bus, floating → 16-bit host bus.
22 SD15/WAKE bidirectional 16-bit mode: processor data bus bit 15. 8-bit mode: WAKE output - pulses on a wake-up event. Also latched at reset as a strap for CS# polarity in 8-bit mode (pull-high → CS# active-high, float → CS# active-low).
23 VDD power_in 3.3 V digital supply input.
24 SD14/LED3 bidirectional 16-bit mode: processor data bus bit 14. 8-bit mode: LED3 full-duplex LED output (open-drain low when internal PHY is full-duplex; LED mode is set in EEPROM).
25 SD13/GP6 bidirectional 16-bit mode: processor data bus bit 13. 8-bit mode: GP6 general-purpose output (register 1Fh); also acts at reset as a strap defining INT output type (pull-high → open-drain, float → force/push-pull).
26 SD12/GP5 bidirectional 16-bit mode: processor data bus bit 12. 8-bit mode: GP5 general-purpose output driven by register 1Fh.
27 SD11/GP4 bidirectional 16-bit mode: processor data bus bit 11. 8-bit mode: GP4 general-purpose output driven by register 1Fh.
28 SD10/GP3 bidirectional 16-bit mode: processor data bus bit 10. 8-bit mode: GP3 general-purpose I/O (registers GPCR/GPR); default is input.
29 SD9/GP2 bidirectional 16-bit mode: processor data bus bit 9. 8-bit mode: GP2 general-purpose I/O (registers GPCR/GPR); default is input.
30 VDD power_in 3.3 V digital supply input.
31 SD8/GP1 bidirectional 16-bit mode: processor data bus bit 8. 8-bit mode: GP1 general-purpose I/O (registers GPCR/GPR); default is input.
32 CMD input Command type: high selects the DATA port for the current cycle, low selects the INDEX (address) port. Internal pull-down ~60 kΩ.
33 GND power_in Digital ground.
34 INT output Interrupt request to the host. High-active by default; polarity may be flipped by EEPROM setting or by the EECK strap. Internal pull-down ~60 kΩ.
35 IOR# input Processor read strobe. Low-active by default; polarity configurable via EEPROM. Internal pull-down ~60 kΩ.
36 IOW# input Processor write strobe. Low-active by default; polarity configurable via EEPROM. Internal pull-down ~60 kΩ.
37 CS# input Chip-select to the DM9000C/CI host interface. Low-active by default; polarity configurable via EEPROM (and by the WAKE strap in 8-bit mode). Internal pull-down ~60 kΩ.
38 LED2 bidirectional Link/Activity LED for the internal PHY (behavior depends on LED mode set in EEPROM word 7). Function is disabled when the pin is repurposed for the WOL output.
39 LED1 bidirectional Speed LED for the internal PHY: low drive indicates 100 Mb/s; floats in 10 Mb/s mode.
40 PWRST# input Active-low power-on reset. The DM9000C/CI is ready ~5 µs after this pin is deasserted.
41 TEST input Operation-mode/test pin. Tie to ground in normal application.
42 VDD power_in 3.3 V digital supply input.
43 X2 output 25 MHz crystal oscillator output (connect to one leg of the crystal, or leave floating if X1 is driven by an external clock).
44 X1 input 25 MHz crystal oscillator input.
45 GND power_in Digital ground.
46 SD input Fiber-optic Signal Detect (PECL input). Indicates whether the fiber-optic receive pair is receiving valid levels; tie appropriately when unused.
47 RXGND power_in Analog ground for the RX/receive PHY block (second RXGND pin).
48 BGGND power_in Band-gap analog ground return.

Key specifications

Parameter Value
Manufacturer DAVICOM
Package LQFP-48(7x7)
Category Interface
Pins 48

Ordering variants

Same part, different packaging or reel option.

  • DM9000CEP
  • DM9000CEPCIEP

CAD (KiCad official)

  • Symbol: DM9000CEP
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: dm9000cep-etched.step / dm9000cep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dm9000cep.step / dm9000cep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: DAVICOM datasheet (63 pp, sha256 ee55ca9f9a5216f5, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF