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DM9000AEP

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DAVICOM Ethernet Controllers, LQFP-48(7x7). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs dm9000aep: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers dm9000aep: viewers · Ray
dm9000aep-etched.fit.json dm9000aep: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dm9000aep-etched.glb dm9000aep: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dm9000aep-etched.step dm9000aep: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dm9000aep.glb Publish 0.1.0 · Ray
dm9000aep.kicad_mod Publish 0.1.0 · Ray
dm9000aep.kicad_sym Publish 0.1.0 · Ray
dm9000aep.lbr Publish 0.1.0 · Ray
dm9000aep.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json dm9000aep: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md dm9000aep: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

DM9000AEP

DAVICOM · Ethernet Controllers · LQFP-48(7x7)

DM9000AEP from DAVICOM, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BGRES bidirectional Bandgap reference pin. Connect an external bias resistor (typically to BGGND) per the application circuit to set the internal bandgap current reference.
2 RXVDD25 power_out 2.5V regulated power output for the TP receive analog block. Bypass to RXGND with a decoupling capacitor; not a supply input.
3 RX+ bidirectional Twisted-pair receive positive (10/100BASE-TX). Connect through the magnetics to the RJ45 receive pair; may swap with RX- in Auto-MDIX mode.
4 RX- bidirectional Twisted-pair receive negative (10/100BASE-TX). Connect through the magnetics to the RJ45 receive pair; may swap with RX+ in Auto-MDIX mode.
5 RXGND power_in Receive analog ground return for the twisted-pair receive block.
6 TXGND power_in Transmit analog ground return for the twisted-pair transmit block.
7 TX+ bidirectional Twisted-pair transmit positive (10/100BASE-TX). Drives the RJ45 transmit pair through the magnetics; may swap with TX- in Auto-MDIX mode.
8 TX- bidirectional Twisted-pair transmit negative (10/100BASE-TX). Drives the RJ45 transmit pair through the magnetics; may swap with TX+ in Auto-MDIX mode.
9 TXVDD25 power_out 2.5V regulated power output for the TP transmit analog block. Bypass to TXGND with a decoupling capacitor; not a supply input.
10 SD7 bidirectional Processor data bus bit 7 (host interface). 8mA I/O with internal pull-down; drive strength selectable via BUSCR (reg 38H).
11 SD6 bidirectional Processor data bus bit 6 (host interface). 8mA I/O with internal pull-down.
12 SD5 bidirectional Processor data bus bit 5 (host interface). 8mA I/O with internal pull-down.
13 SD4 bidirectional Processor data bus bit 4 (host interface). 8mA I/O with internal pull-down.
14 SD3 bidirectional Processor data bus bit 3 (host interface). 8mA I/O with internal pull-down.
15 GND power_in Digital ground return.
16 SD2 bidirectional Processor data bus bit 2 (host interface). 8mA I/O with internal pull-down.
17 SD1 bidirectional Processor data bus bit 1 (host interface). 8mA I/O with internal pull-down.
18 SD0 bidirectional Processor data bus bit 0 (host interface). 8mA I/O with internal pull-down.
19 EEDIO bidirectional Serial EEPROM data I/O (Microwire 93C46-style). 8mA I/O with internal pull-down; used to auto-load MAC, vendor/product ID, and pin polarity config.
20 EECK output Serial EEPROM clock output. Also a strap pin at power-up: pulled high selects INT active-low, floating (default) selects INT active-high.
21 EECS output Serial EEPROM chip select output. Also a strap pin at power-up: pulled high selects 8-bit host data bus, floating (default) selects 16-bit.
22 SD15/WAKE bidirectional Dual-function pin. In 16-bit host mode this is processor data bus bit 15 (I/O, 8mA). In 8-bit host mode (EECS strapped high) it is WAKE, an output that asserts on a wake-up event; it is also strap-sampled at power-up to select CS# polarity (pulled high = CS# active high, floating = CS# active low).
23 VDD power_in Digital 3.3V supply input. Bypass locally with a decoupling capacitor.
24 SD14/LED3 bidirectional Dual-function pin. In 16-bit host mode this is processor data bus bit 14 (I/O, 8mA). In 8-bit host mode it is LED3, a 16mA open-drain-style output that drives the full-duplex or 10M indicator LED per the EEPROM-selected LED mode.
25 SD13/GP6 bidirectional Dual-function pin. In 16-bit host mode this is processor data bus bit 13 (I/O, 8mA). In 8-bit host mode it is GP6, a general-purpose output (8mA) controlled by register 1Fh; also strap-sampled at power-up to select INT output type (pulled high = open-drain, floating = force/push-pull).
26 SD12/GP5 bidirectional Dual-function pin. In 16-bit host mode this is processor data bus bit 12 (I/O, 8mA). In 8-bit host mode it is GP5, a general-purpose output (8mA) driven from register 1Fh.
27 SD11/GP4 bidirectional Dual-function pin. In 16-bit host mode this is processor data bus bit 11 (I/O, 8mA). In 8-bit host mode it is GP4, a general-purpose output (8mA) driven from register 1Fh.
28 SD10/GP3 bidirectional Dual-function pin. In 16-bit host mode this is processor data bus bit 10 (I/O, 8mA). In 8-bit host mode it is GP3, a general-purpose I/O (8mA, default input) programmed via the GPCR (1Eh) and GPR (1Fh) registers.
29 SD9/GP2 bidirectional Dual-function pin. In 16-bit host mode this is processor data bus bit 9 (I/O, 8mA). In 8-bit host mode it is GP2, a general-purpose I/O (8mA, default input) programmed via GPCR and GPR.
30 VDD power_in Digital 3.3V supply input. Bypass locally with a decoupling capacitor.
31 SD8/GP1 bidirectional Dual-function pin. In 16-bit host mode this is processor data bus bit 8 (I/O, 8mA). In 8-bit host mode it is GP1, a general-purpose I/O (8mA, default input) programmed via GPCR and GPR.
32 CMD input Command-type / address-strobe input for the host bus. High = the current cycle accesses the DATA port; low = the current cycle accesses the INDEX (address) port. Internal pull-down.
33 GND power_in Digital ground return.
34 INT output Interrupt request to host. 8mA output, active-high by default; polarity is programmable via EEPROM or the EECK strap pin, and output type (push-pull vs open-drain) is set in 8-bit mode by the GP6 strap.
35 IOR# input Processor read strobe. Active-low by default; polarity is programmable via EEPROM. Internal pull-down.
36 IOW# input Processor write strobe. Active-low by default; polarity is programmable via EEPROM. Internal pull-down.
37 CS# input Chip select. Active-low by default; polarity is programmable via EEPROM (and by the WAKE strap pin in 8-bit mode). Internal pull-down.
38 LED2 output Link/Activity LED driver, 16mA. LED mode 1 = combined link + carrier-sense of the internal PHY; LED mode 0 = carrier-sense only. In 16-bit mode this pin can alternately be strapped as ISA IOWAIT or WAKE per EEPROM.
39 LED1 output Speed LED driver, 16mA. Low = internal PHY operating at 100 Mbps; floating = 10 Mbps. In 16-bit mode this pin can alternately act as ISA bus IO16 per EEPROM setting.
40 PWRST# input Active-low power-on reset. The DM9000A is ready 5 us after this pin is deasserted.
41 TEST input Operation-mode / test-mode select. Tie to ground for normal application; factory test use only.
42 VDD power_in Digital 3.3V supply input. Bypass locally with a decoupling capacitor.
43 X2 output 25 MHz crystal oscillator output. Connect to the far side of the parallel-resonant 25 MHz crystal (with its loading capacitors), or leave floating if X1 is driven by an external clock.
44 X1 input 25 MHz crystal oscillator input, or single-ended clock input from an external 25 MHz source.
45 GND power_in Digital ground return.
46 SD input Fiber-optic Signal Detect input (PECL). Indicates whether the fiber receive pair is seeing a valid signal; used only in the optional 100M fiber interface mode.
47 RXGND power_in Second receive analog ground return; tie together with pin 5 (RXGND) at the analog ground.
48 BGGND power_in Bandgap analog ground return for the BGRES reference.

Key specifications

Parameter Value
Manufacturer DAVICOM
Package LQFP-48(7x7)
Category Interface
Pins 48

Ordering variants

Same part, different packaging or reel option.

  • DM9000AEP

CAD (KiCad official)

  • Symbol: DM9000AEP
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: dm9000aep-etched.step / dm9000aep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dm9000aep.step / dm9000aep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: DAVICOM datasheet (60 pp, sha256 ddbd914643835170, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF