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DIX4192IPFBRQ1

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Texas Instruments Audio Interface ICs, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DIX4192IPFBRQ1

Texas Instruments · Audio Interface ICs · TQFP-48(7x7)

DIX4192IPFBRQ1 from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RX1+ input Line receiver 1 noninverting input; per-pin line receiver input voltage is limited to (VDD33 + 0.3) VPP.
2 RX1- input Line receiver 1 inverting input; per-pin line receiver input voltage is limited to (VDD33 + 0.3) VPP.
3 RX2+ input Line receiver 2 noninverting input; per-pin line receiver input voltage is limited to (VDD33 + 0.3) VPP.
4 RX2- input Line receiver 2 inverting input; per-pin line receiver input voltage is limited to (VDD33 + 0.3) VPP.
5 RX3+ input Line receiver 3 noninverting input; per-pin line receiver input voltage is limited to (VDD33 + 0.3) VPP.
6 RX3- input Line receiver 3 inverting input; per-pin line receiver input voltage is limited to (VDD33 + 0.3) VPP.
7 RX4+ input Line receiver 4 noninverting input; per-pin line receiver input voltage is limited to (VDD33 + 0.3) VPP.
8 RX4- input Line receiver 4 inverting input; per-pin line receiver input voltage is limited to (VDD33 + 0.3) VPP.
9 VCC power_in DIR comparator and PLL power supply, 3.3 V nominal; recommended range 3 V to 3.6 V.
10 AGND power_in DIR comparator and PLL power-supply ground.
11 LOCK output DIR PLL lock flag, active low; asserted only when both the AES3 decoder and PLL2 indicate lock.
12 RXCKO output DIR recovered master clock, tri-state output.
13 RXCKI input DIR reference clock input.
14 NC unconnected No internal signal connection; internally bonded to ESD pad.
15 NC unconnected No internal signal connection; internally bonded to ESD pad.
16 DGND1 power_in Digital core ground.
17 VDD18 power_in Digital core supply, 1.8 V nominal; recommended range 1.65 V to 1.95 V.
18 CPM input Control port mode select: 0 = SPI mode, 1 = I2C mode.
19 CS/A0 input Active-low chip select for SPI mode, or programmable slave address bit for I2C mode; CS must be forced low to read or write registers.
20 CCLK/SCL input Serial data clock for SPI mode (data latched on rising edge) or I2C mode.
21 CDIN/A1 input SPI serial data input (ignored when CS is high) or programmable slave address bit for I2C mode.
22 CDOUT/SDA bidirectional SPI serial data output (forced high-impedance when CS is high) or serial data I/O for I2C mode.
23 INT output Interrupt flag, open-drain active low; requires a pullup to VIO, with 10 kΩ stated as sufficient for most applications.
24 RST input Reset input, active low.
25 MCLK input Master clock input; frequency 1 MHz to 27.7 MHz with 45% to 55% duty cycle.
26 GPO1 output General-purpose output 1, programmable via control registers 0x1B to 0x1E to a static level or an internal logic node.
27 GPO2 output General-purpose output 2, programmable via control registers 0x1B to 0x1E to a static level or an internal logic node.
28 GPO3 output General-purpose output 3, programmable via control registers 0x1B to 0x1E to a static level or an internal logic node.
29 GPO4 output General-purpose output 4, programmable via control registers 0x1B to 0x1E to a static level or an internal logic node.
30 DGND2 power_in DIR line receiver bias and DIT line driver digital ground.
31 TX- output DIT line driver inverting output.
32 TX+ output DIT line driver noninverting output.
33 VDD33 power_in DIR line receiver bias and DIT line driver supply, 3.3 V nominal; recommended range 3 V to 3.6 V.
34 AESOUT output DIT buffered AES3-encoded CMOS logic-level output; forced low when AESOFF is set.
35 BLS bidirectional DIT block start clock; acts as input or output as selected by the BLSM register bit.
36 SYNC output DIT internal sync clock output.
37 BCKA bidirectional Audio serial port A bit clock.
38 LRCKA bidirectional Audio serial port A left/right clock.
39 SDINA input Audio serial port A data input.
40 SDOUTA output Audio serial port A data output.
41 NC unconnected No internal signal connection; internally bonded to ESD pad.
42 VIO power_in Logic I/O supply, 1.65 V to 3.6 V.
43 DGND3 power_in Logic I/O ground.
44 BGND power_in Substrate ground; connect to AGND (pin 10).
45 SDOUTB output Audio serial port B data output.
46 SDINB input Audio serial port B data input.
47 LRCKB bidirectional Audio serial port B left/right clock.
48 BCKB bidirectional Audio serial port B bit clock.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: DIX4192IPFBRQ1
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: dix4192ipfbrq1-etched.step / dix4192ipfbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dix4192ipfbrq1.step / dix4192ipfbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (70 pp, sha256 dde4e8a8e4e4e262, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF