DIX4192IPFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RX1+	input	Line receiver 1 noninverting input; differential input sensitivity is 150 mV to 200 mV across the RX1+/RX1- pair.
2	RX1-	input	Line receiver 1 inverting input; differential input sensitivity is 150 mV to 200 mV across the RX1+/RX1- pair.
3	RX2+	input	Line receiver 2 noninverting input; differential input sensitivity is 150 mV to 200 mV across the RX2+/RX2- pair.
4	RX2-	input	Line receiver 2 inverting input; differential input sensitivity is 150 mV to 200 mV across the RX2+/RX2- pair.
5	RX3+	input	Line receiver 3 noninverting input; differential input sensitivity is 150 mV to 200 mV across the RX3+/RX3- pair.
6	RX3-	input	Line receiver 3 inverting input; differential input sensitivity is 150 mV to 200 mV across the RX3+/RX3- pair.
7	RX4+	input	Line receiver 4 noninverting input; differential input sensitivity is 150 mV to 200 mV across the RX4+/RX4- pair.
8	RX4-	input	Line receiver 4 inverting input; differential input sensitivity is 150 mV to 200 mV across the RX4+/RX4- pair.
9	VCC	power_in	DIR comparator and PLL power supply, 3.3 V nominal (3.0 V to 3.6 V recommended operating range).
10	AGND	power_in	DIR comparator and PLL power-supply ground; BGND (pin 44) must be connected to this pin by PCB trace.
11	LOCK	output	DIR PLL lock flag, active low; asserted only when both the AES3 decoder and PLL2 indicate lock.
12	RXCKO	tri_state	DIR recovered master clock output, tri-state; disabled and forced to high-impedance by default (RXCKOE = 0).
13	RXCKI	input	DIR reference clock input, 3.5 MHz to 27.7 MHz (duty cycle 45% to 55%).
14	NC	unconnected	No internal signal connection; internally bonded to ESD pad.
15	NC	unconnected	No internal signal connection; internally bonded to ESD pad.
16	DGND1	power_in	Digital core ground.
17	VDD18	power_in	Digital core supply, 1.8 V nominal (1.65 V to 1.95 V).
18	CPM	input	Control port mode select: 0 selects SPI mode, 1 selects I2C mode.
19	CS/A0	input	Active-low chip select for SPI mode; programmable slave address bit A0 for I2C mode.
20	CCLK/SCL	input	Serial data clock for SPI mode (CCLK) or I2C bus clock (SCL).
21	CDIN/A1	input	SPI serial data input in SPI mode, or programmable slave address bit A1 in I2C mode.
22	CDOUT/SDA	bidirectional	SPI serial data output (tri-state, high-impedance when CS is high) in SPI mode, or I2C serial data I/O (SDA) in I2C mode.
23	INT	output	Interrupt flag, open-drain and active low; requires a pullup to VIO (10 kΩ suggested).
24	RST	input	Asynchronous active-low reset; the low pulse must be at least 500 ns and no read/write may occur for 500 µs after the rising edge.
25	MCLK	input	Master clock input, 1 MHz to 27.7 MHz (duty cycle 45% to 55%).
26	GPO1	output	General-purpose output 1, forced low by default and configurable via control register 0x1B to static or internal logic signals.
27	GPO2	output	General-purpose output 2, forced low by default and configurable via control register 0x1C to static or internal logic signals.
28	GPO3	output	General-purpose output 3, forced low by default and configurable via control register 0x1D to static or internal logic signals.
29	GPO4	output	General-purpose output 4, forced low by default and configurable via control register 0x1E to static or internal logic signals.
30	DGND2	power_in	DIR line receiver bias and DIT line driver digital ground.
31	TX-	output	DIT line driver inverting output; forced low when TXOFF is set.
32	TX+	output	DIT line driver noninverting output; forced low when TXOFF is set.
33	VDD33	power_in	DIR line receiver bias and DIT line driver supply, 3.3 V nominal (3.0 V to 3.6 V).
34	AESOUT	output	DIT buffered AES3-encoded CMOS logic-level output; forced low when AESOFF is set.
35	BLS	bidirectional	DIT block start clock; configured as input by default and may be set as output via the BLSM bit.
36	SYNC	output	DIT internal sync clock output; its rising edge aligns with the start of each AES3 frame.
37	BCKA	bidirectional	Audio serial Port A bit clock; input in slave mode, output in master mode (64 × LRCKA).
38	LRCKA	bidirectional	Audio serial Port A left/right word clock; input in slave mode, output in master mode, operating at fS up to 216 kHz.
39	SDINA	input	Audio serial Port A data input, sampled on the rising edge of BCKA.
40	SDOUTA	output	Audio serial Port A data output, clocked out on the falling edge of BCKA; forced low when AMUTE is set.
41	NC	unconnected	No internal signal connection; internally bonded to ESD pad.
42	VIO	power_in	Logic I/O supply, 1.65 V to 3.6 V.
43	DGND3	power_in	Logic I/O ground.
44	BGND	power_in	Substrate ground; connect to AGND (pin 10).
45	SDOUTB	output	Audio serial Port B data output, clocked out on the falling edge of BCKB; forced low when BMUTE is set.
46	SDINB	input	Audio serial Port B data input, sampled on the rising edge of BCKB.
47	LRCKB	bidirectional	Audio serial Port B left/right word clock; input in slave mode, output in master mode, operating at fS up to 216 kHz.
48	BCKB	bidirectional	Audio serial Port B bit clock; input in slave mode, output in master mode (64 × LRCKB).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-48(7x7)
Category	Interface
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power supply VDD18 (absolute maximum)	VDD18	-0.3		2	V		5
Power supply VDD33 (absolute maximum)	VDD33	-0.3		4	V		5
Power supply VIO (absolute maximum)	VIO	-0.3		4	V		5
Power supply VCC (absolute maximum)	VCC	-0.3		4	V		5
Digital input voltage (digital logic pins)		-0.3			V		5
Input current (all pins except power and ground)		-10		10	mA		5
Ambient operating temperature		-40		85	°C		5
Storage temperature	Tstg	-65		150	°C		5
Supply voltage VDD18 (recommended)	VDD18	1.65	1.8	1.95	V		6
Supply voltage VDD33 (recommended)	VDD33	3	3.3	3.6	V		6
Supply voltage VIO (recommended)	VIO	1.65	3.3	3.6	V		6
Supply voltage VCC (recommended)	VCC	3	3.3	3.6	V		6
Low-level input voltage	VIL	0			V		6
Low-level output voltage	VOL	0			V		6
High-level input current	IIH	0.5		25	μA	IO = -4 mA, MUTE, SDINA, and SDINB pins	6
High-level input current	IIH	0.5		10	μA	IO = -4 mA, all other pins	6
Low-level input current	IIL	0.5		10	μA	IO = 4 mA	6
Master clock input (MCLK) frequency	fMCLK	1		27.7	MHz		6
Master clock input (MCLK) duty cycle	fMCLKD	45		55	%		6
PLL lock range		20		216	kHz	TA = 25°C	6
Reference clock input (RXCKI) frequency	fRXCKI	3.5		27.7	MHz		6
Reference clock input (RXCKI) duty cycle	fRXCKID	45		55	%		6
Recovered clock output (RXCKO) frequency	fRXCKO	3.5		27.7	MHz		6
Recovered clock output (RXCKO) duty cycle	fRXCKOD	45		55	%		7
LRCK clock frequency	fLRCK	0		216	kHz		7
BCK clock frequency	fBCK	0		13.824	MHz		7
Serial clock (CCLK) frequency	fCCLK	0		40	MHz	SPI mode	7
Clock frequency SCL (standard mode)	fSCL	0		100	kHz	I2C standard mode	8
Data hold time (standard mode)	tHDDAT	0		3.45	μs		8
SCL clock frequency (fast mode)	fSCL	0		400	kHz	I2C fast mode	8
Data hold time (fast mode)	tHDDAT	0		0.9	μs	I2C fast mode	8
Rise time for both SDA and SCL (fast mode)	tR			300	ns	I2C fast mode	8
Fall time for both SDA and SCL (fast mode)	tF			300	ns	I2C fast mode	8
Spike pulse width suppressed by input filter	tSP	0		50	ns	I2C fast mode	8
Junction-to-ambient thermal resistance	RθJA		62		°C/W		6
Junction-to-case (top) thermal resistance	RθJC(top)		12.8		°C/W		6
Junction-to-board thermal resistance	RθJB		27.9		°C/W		6
Junction-to-top characterization parameter	ψJT		0.3		°C/W		6
Junction-to-board characterization parameter	ψJB		27.6		°C/W		6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		nickel	SD NI A (pin 39) or SDINB (pin 4 )6 LRCKA (pin 3 ) or8 LRCKB ( i 47) p n	14

CAD (KiCad official)

Symbol: DIX4192IPFBR
Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: dix4192ipfbr-etched.step / dix4192ipfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dix4192ipfbr.step / dix4192ipfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (71 pp, sha256 bd404824f133bc57, retrieved 2026-11-10, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DIX4192IPFBR

Verified DIX4192IPFBR

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3D Model

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