component

DIO7002AST5

Public Made by Adom

by adom

DIOO AC-DC Controllers and Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs dio7002ast5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers dio7002ast5: viewers · Ray
dio7002ast5-etched.fit.json dio7002ast5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dio7002ast5-etched.glb dio7002ast5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dio7002ast5-etched.step dio7002ast5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dio7002ast5.glb Publish 0.1.0 · Ray
dio7002ast5.kicad_mod Publish 0.1.0 · Ray
dio7002ast5.kicad_sym Publish 0.1.0 · Ray
dio7002ast5.lbr Publish 0.1.0 · Ray
dio7002ast5.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json dio7002ast5: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md dio7002ast5: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

DIO7002AST5

DIOO · AC-DC Controllers and Regulators · SOT-23-5

DIO7002AST5 from DIOO, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Switched power output pin. Decouple with a 10 µF ceramic capacitor to GND. Delivers up to 2.5 A of load current from the internal power FET (typ. 70 mΩ RDS(ON)).
2 GND power_in Ground reference for the device.
3 ISET input Current-limit programming pin. An external resistor RSET from ISET to GND sets the current limit per ILIM(A) = 6800 / RSET(Ω). Typical 6.8 kΩ → 1 A limit; do not program above 2.5 A.
4 EN input ON/OFF control input. For DIO7002AST5 (A variant) this pin is active-high: logic high enables the switch, logic low shuts it down. Compatible with TTL/CMOS logic (VEN(H) ≥ 2 V, VEN(L) ≤ 0.8 V). Do not leave floating.
5 IN power_in Input supply pin, 2.7 V to 5.5 V. Decouple with a 10 µF ceramic capacitor to GND to prevent input droop during hot-plug and improve short-circuit ruggedness.

Key specifications

Parameter Value
Manufacturer DIOO
Package SOT-23-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • DIO7002AST5
  • DIO7002AST5BST5

CAD (KiCad official)

  • Symbol: DIO7002AST5
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: dio7002ast5-etched.step / dio7002ast5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dio7002ast5.step / dio7002ast5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: DIOO datasheet (12 pp, sha256 ba29909df52621d2, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF