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DGD2190MS8-13

Diodes Incorporated · Gate Drive ICs · SO-8

DGD2190MS8-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	HIN	input	Logic input for the high-side gate driver output, in phase with HO; TTL/CMOS compatible (down to 3.3V) with Schmitt trigger and internal pull-down, 0 to 5V recommended.
2	LIN	input	Logic input for the low-side gate driver output, in phase with LO; TTL/CMOS compatible (down to 3.3V) with Schmitt trigger and internal pull-down, 0 to 5V recommended.
3	COM	power_in	Low-side and logic return (ground).
4	LO	output	Low-side gate drive output, capable of 4.5A typ. sink/source, swinging from 0 to VCC.
5	VCC	power_in	Low-side and logic fixed supply, recommended 10V to 20V (absolute maximum 24V) with undervoltage lockout.
6	VS	power_in	High-side floating supply return (offset), recommended up to 600V.
7	HO	output	High-side gate drive output, capable of 4.5A typ. sink/source, swinging between VS and VB.
8	VB	power_in	High-side floating supply, recommended VS+10V to VS+20V (absolute maximum 624V) with undervoltage lockout.

Key specifications

Parameter	Value
Manufacturer	Diodes Incorporated
Package	SO-8
Category	Power Supply Chip
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
High-Side Floating Supply Voltage	VB	-0.3		624	V	TA = +25°C	3
Offset Supply Voltage Transient	dVS/dt			50	V/ns	TA = +25°C	3
Low-Side and Logic Fixed Supply Voltage	VCC	-0.3		24	V	TA = +25°C	3
Low-Side Output Voltage (min only)	VLO	-0.3			V	max is VCC +0.3	3
Logic Input Voltage (HIN and LIN) (min only)	VIN	-0.3			V	max is VCC +0.3	3
Power Dissipation Linear Derating Factor	PD			0.625	W	JEDEC 2-layer FR-4 board, TA = +25°C	3
Operating Temperature	TJ			150	°C	TA = +25°C	3
Storage Temperature Range	TSTG	-55		150	°C		3
Low-Side Fixed Supply Voltage	VCC	10		20	V		3
High-Side Floating Supply Offset Voltage	VS			600	V	Logic operation for VS of -5V to +600V	3
Low-Side Output Voltage (min only)	VLO	0			V	max is VCC	3
Logic Input Voltage (HIN and LIN)	VIN	0		5	V		3
Ambient Temperature	TA	-40		125	°C		3
Logic 1 Input Voltage	VIH	2.5			V	VCC = 10V to 20V	4
Logic 0 Input Voltage	VIL			0.8	V	VCC = 10V to 20V	4
High Level Output Voltage, VBIAS - VO	VOH			0.1	V	IO = 0mA	4
Low Level Output Voltage, VO	VOL			0.035	V	IO = 0mA	4
Offset Supply Leakage Current	ILK			50	µA	VB = VS = 600V	4
Quiescent VBS Supply Current	IBSQ		45	80	µA	VIN = 0V or 5V	4
Quiescent VCC Supply Current	ICCQ		75	200	µA	VIN = 0V or 5V	4
Logic 1 Input Bias Current	IIN+		25	50	µA	VIN = 5V	4
Logic 0 Input Bias Current	IIN-		1	2	µA	VIN = 0V	4
VBS Supply Undervoltage Positive Going Threshold	VBSUV+	7.6	8.4	9.8	V		4
VBS Supply Undervoltage Negative Going Threshold	VBSUV-	6.9	7.8	9	V		4
VCC Supply Undervoltage Positive Going Threshold	VCCUV+	7.6	8.4	9.8	V		4
VCC Supply Undervoltage Negative Going Threshold	VCCUV-	6.9	7.8	9	V		4
Output High Short Circuit Pulsed Current	IO+	3.5	4.5		A	VO = 0V, PW ≤ 10ms	4
Output Low Short Circuit Pulsed Current	IO-	3.5	4.5		A	VO = 15V, PW ≤ 10ms	4
Turn-On Propagation Delay	tON		140	200	ns	VS = 0V, CL = 1000pF	4
Turn-Off Propagation Delay	tOFF		140	200	ns	VS = 0V, CL = 1000pF	4
Delay Matching, HO & LO Turn On/Off	tDM			50	ns	CL = 1000pF	4
Turn-On Rise Time	tR		25	50	ns	VS = 0V, CL = 1000pF	4
Turn-Off Fall Time	tF		20	45	ns	VS = 0V, CL = 1000pF	4
VCC and VBS Undervoltage Hysteresis (VCC)	VCCUVH		0.6		V		4
VCC and VBS Undervoltage Hysteresis (VBS)	VBSUVH		0.6		V		4
Thermal Resistance, Junction to Ambient	RθJA		200		°C/W	JEDEC 2-layer FR-4 board	3
Thermal Resistance, Junction to Case	RθJC		45		°C/W	JEDEC 2-layer FR-4 board	3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	 Terminals: Finish, Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208	1

CAD (KiCad official)

Symbol: DGD2190MS8-13
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SO-8 (KiCad packages3D, STEP)
3D model files: dgd2190ms8-13-etched.step / dgd2190ms8-13-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dgd2190ms8-13.step / dgd2190ms8-13.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Diodes Incorporated datasheet (11 pp, sha256 d525729d511579fc, retrieved 2026-10-24, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF