component
DGD0280WT-7
Public Made by Adomby adom
Diodes Incorporated Gate Drive ICs, TSOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
DGD0280WT-7
Diodes Incorporated · Gate Drive ICs · TSOT-23-5
DGD0280WT-7 from Diodes Incorporated, in a TSOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low-side fixed supply input, recommended operating range 4.5 V to 18 V, with absolute maximum of -0.3 V to +22 V and internal UVLO that turns the output off when VCC falls below the operating range. |
| 2 | COM | power_in | Supply return (ground) for the driver, which is the reference for the logic input, the gate drive output and the LDO. |
| 3 | IN | input | Logic input, in phase with OUT, compatible with TTL and CMOS levels down to 3.3 V, with recommended range 0 V to 5 V, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 4 | 3V3 | power_out | Integrated LDO regulator output at 3.3 V (3.267 V to 3.333 V at IOUT = 10 mA), capable of supplying up to 15 mA. |
| 5 | OUT | output | Non-inverted gate drive output for the external MOSFET or IGBT, with 2.5 A source and 2.8 A sink peak current capability, and an output voltage range of -0.3 V to VCC + 0.3 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | TSOT-23-5 |
| Category | Power Supply Chip |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Low-Side Fixed Supply Voltage | VCC | -0.3 | 22 | V | 3 | ||
| Output Voltage (OUT) | VOUT | -0.3 | V | 3 | |||
| Logic Input Voltage (IN) | VIN | -5 | V | 3 | |||
| Supply Voltage | VCC | 4.5 | 18 | V | 3 | ||
| Output Voltage (OUT) | VOUT | 0 | V | 3 | |||
| Logic Input Voltage (IN) | VIN | 0 | 5 | V | 3 | ||
| Ambient Temperature | TA | -40 | 125 | °C | 3 | ||
| Logic "1" Input Voltage | VIH | 2 | V | 4 | |||
| Logic "0" Input Voltage | VIL | 0.8 | V | 4 | |||
| Logic "1" Input Bias Current | IIN+ | 7.5 | 20 | µA | VIN = 3V | 4 | |
| Logic "0" Input Bias Current | IIN- | 1 | µA | VIN = 0V | 4 | ||
| Quiescent VCC Supply Current | ICCQ | 250 | µA | Inputs Open | 4 | ||
| VCC Supply Undervoltage Positive Going Threshold | VCCUV+ | 4.5 | 4.75 | 5 | V | 4 | |
| VCC Supply Undervoltage Negative Going Threshold | VCCUV- | 4.2 | 4.5 | 4.8 | V | 4 | |
| LDO Output Voltage | VLDO | 3.267 | 3.3 | 3.333 | V | IOUT = 10mA | 4 |
| LDO Line Regulation | VLDO_LINE | 21 | 38 | mV | VCC = 5V to 18V, IOUT = 10mA | 4 | |
| LDO Load Regulation | VLDO_LOAD | 10 | mV | VCC = 12V, IOUT = 0.1mA to 10mA | 4 | ||
| LDO Current Limit | ILDO_LIM | 20 | 68 | mA | RL = 0Ω | 4 | |
| Turn-On Rise Time | tr | 20 | 35 | ns | CL = 1000pF | 4 | |
| Turn-Off Fall Time | tf | 15 | 35 | ns | CL = 1000pF | 4 | |
| Turn-On Propagation Delay | tON | 20 | 35 | 50 | ns | 4 | |
| Turn-Off Propagation Delay | tOFF | 15 | 30 | 50 | ns | 4 | |
| Storage Temperature Range | TSTG | -55 | 150 | °C | 3 | ||
| Operating Temperature | TJ | 150 | °C | 3 | |||
| Lead Temperature (Soldering) | TL | 300 | °C | Soldering, 10s | 3 | ||
| Power Dissipation Linear Derating Factor | PD | 0.89 | W | Note 5: standard JEDEC 2-layer FR-4 board with minimum recommended pad layout | 3 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 117 | °C/W | Note 5: standard JEDEC 2-layer FR-4 board with minimum recommended pad layout | 3 | ||
| Thermal Resistance, Junction to Case | RθJC | 12.5 | °C/W | Note 5: standard JEDEC 2-layer FR-4 board with minimum recommended pad layout | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Terminals: Finish, Matte Tin Plated Leads. Solderable per MIL-STD-202, Method 208 | 1 |
CAD (KiCad official)
- Symbol:
DGD0280WT-7 - Footprint:
Package_TO_SOT_SMD:TSOT-23-5 - 3D model: TSOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
dgd0280wt-7-etched.step/dgd0280wt-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dgd0280wt-7.step/dgd0280wt-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (11 pp, sha256
eb379e9b1799f801, retrieved 2026-10-24, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DGD0280WT-7
**Diodes Incorporated** · Gate Drive ICs · TSOT-23-5
DGD0280WT-7 from Diodes Incorporated, in a TSOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low-side fixed supply input, recommended operating range 4.5 V to 18 V, with absolute maximum of -0.3 V to +22 V and internal UVLO that turns the output off when VCC falls below the operating range. |
| 2 | COM | power_in | Supply return (ground) for the driver, which is the reference for the logic input, the gate drive output and the LDO. |
| 3 | IN | input | Logic input, in phase with OUT, compatible with TTL and CMOS levels down to 3.3 V, with recommended range 0 V to 5 V, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 4 | 3V3 | power_out | Integrated LDO regulator output at 3.3 V (3.267 V to 3.333 V at IOUT = 10 mA), capable of supplying up to 15 mA. |
| 5 | OUT | output | Non-inverted gate drive output for the external MOSFET or IGBT, with 2.5 A source and 2.8 A sink peak current capability, and an output voltage range of -0.3 V to VCC + 0.3 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | TSOT-23-5 |
| Category | Power Supply Chip |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Low-Side Fixed Supply Voltage | VCC | -0.3 | | 22 | V | | 3 |
| Output Voltage (OUT) | VOUT | -0.3 | | | V | | 3 |
| Logic Input Voltage (IN) | VIN | -5 | | | V | | 3 |
| Supply Voltage | VCC | 4.5 | | 18 | V | | 3 |
| Output Voltage (OUT) | VOUT | 0 | | | V | | 3 |
| Logic Input Voltage (IN) | VIN | 0 | | 5 | V | | 3 |
| Ambient Temperature | TA | -40 | | 125 | °C | | 3 |
| Logic "1" Input Voltage | VIH | 2 | | | V | | 4 |
| Logic "0" Input Voltage | VIL | | | 0.8 | V | | 4 |
| Logic "1" Input Bias Current | IIN+ | | 7.5 | 20 | µA | VIN = 3V | 4 |
| Logic "0" Input Bias Current | IIN- | | | 1 | µA | VIN = 0V | 4 |
| Quiescent VCC Supply Current | ICCQ | | | 250 | µA | Inputs Open | 4 |
| VCC Supply Undervoltage Positive Going Threshold | VCCUV+ | 4.5 | 4.75 | 5 | V | | 4 |
| VCC Supply Undervoltage Negative Going Threshold | VCCUV- | 4.2 | 4.5 | 4.8 | V | | 4 |
| LDO Output Voltage | VLDO | 3.267 | 3.3 | 3.333 | V | IOUT = 10mA | 4 |
| LDO Line Regulation | VLDO_LINE | | 21 | 38 | mV | VCC = 5V to 18V, IOUT = 10mA | 4 |
| LDO Load Regulation | VLDO_LOAD | | | 10 | mV | VCC = 12V, IOUT = 0.1mA to 10mA | 4 |
| LDO Current Limit | ILDO_LIM | 20 | 68 | | mA | RL = 0Ω | 4 |
| Turn-On Rise Time | tr | | 20 | 35 | ns | CL = 1000pF | 4 |
| Turn-Off Fall Time | tf | | 15 | 35 | ns | CL = 1000pF | 4 |
| Turn-On Propagation Delay | tON | 20 | 35 | 50 | ns | | 4 |
| Turn-Off Propagation Delay | tOFF | 15 | 30 | 50 | ns | | 4 |
| Storage Temperature Range | TSTG | -55 | | 150 | °C | | 3 |
| Operating Temperature | TJ | | | 150 | °C | | 3 |
| Lead Temperature (Soldering) | TL | | | 300 | °C | Soldering, 10s | 3 |
| Power Dissipation Linear Derating Factor | PD | | 0.89 | | W | Note 5: standard JEDEC 2-layer FR-4 board with minimum recommended pad layout | 3 |
| Thermal Resistance, Junction to Ambient | RθJA | | 117 | | °C/W | Note 5: standard JEDEC 2-layer FR-4 board with minimum recommended pad layout | 3 |
| Thermal Resistance, Junction to Case | RθJC | | 12.5 | | °C/W | Note 5: standard JEDEC 2-layer FR-4 board with minimum recommended pad layout | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | Terminals: Finish, Matte Tin Plated Leads. Solderable per MIL-STD-202, Method 208 | 1 |
## CAD (KiCad official)
- Symbol: `DGD0280WT-7`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-5`
- 3D model: TSOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `dgd0280wt-7-etched.step` / `dgd0280wt-7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dgd0280wt-7.step` / `dgd0280wt-7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://www.diodes.com/assets/Datasheets/DGD0280WT-7.pdf) (11 pp, sha256 `eb379e9b1799f801`, retrieved 2026-10-24, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dgd0280wt-7-datasheet.pdf)