component
DG453EQ-T1-E3
Public Made by Adomby adom
Vishay Intertech Analog Switches, Multiplexers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DG453EQ-T1-E3
Vishay Intertech · Analog Switches, Multiplexers · TSSOP-16
DG453EQ-T1-E3 from Vishay Intertech, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN1 | input | Digital logic control input for switch S1/D1; TTL/CMOS compatible with 0.8 V and 2.4 V logic thresholds. |
| 2 | D1 | passive | Drain terminal of switch 1; the signal range extends to the supply voltage rails and signals exceeding V+ or V- are clamped by internal diodes. |
| 3 | S1 | passive | Source terminal of switch 1; the analog signal range is ±15 V with dual supplies and the switch conducts equally well in both directions when on. |
| 4 | V- | power_in | Negative analog supply; V+ to V- is rated at 44 V maximum and GND to V- at 25 V maximum. |
| 5 | GND | power_in | Ground reference for the device; GND to V- is rated at 25 V maximum. |
| 6 | S4 | passive | Source terminal of switch 4; the analog signal range is ±15 V with dual supplies and the switch conducts equally well in both directions when on. |
| 7 | D4 | passive | Drain terminal of switch 4; the signal range extends to the supply voltage rails and signals exceeding V+ or V- are clamped by internal diodes. |
| 8 | IN4 | input | Digital logic control input for switch S4/D4; TTL/CMOS compatible with 0.8 V and 2.4 V logic thresholds. |
| 9 | IN3 | input | Digital logic control input for switch S3/D3; TTL/CMOS compatible with 0.8 V and 2.4 V logic thresholds. |
| 10 | D3 | passive | Drain terminal of switch 3; the signal range extends to the supply voltage rails and signals exceeding V+ or V- are clamped by internal diodes. |
| 11 | S3 | passive | Source terminal of switch 3; the analog signal range is ±15 V with dual supplies and the switch conducts equally well in both directions when on. |
| 12 | VL | power_in | Logic supply; per the absolute maximum ratings VL must be kept between (GND - 0.3) V and (V+) + 0.3 V, and the datasheet tests use VL = 5 V. |
| 13 | V+ | power_in | Positive analog supply; V+ to V- is rated at 44 V maximum. |
| 14 | S2 | passive | Source terminal of switch 2; the analog signal range is ±15 V with dual supplies and the switch conducts equally well in both directions when on. |
| 15 | D2 | passive | Drain terminal of switch 2; the signal range extends to the supply voltage rails and signals exceeding V+ or V- are clamped by internal diodes. |
| 16 | IN2 | input | Digital logic control input for switch S2/D2; TTL/CMOS compatible with 0.8 V and 2.4 V logic thresholds. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Signal Range | VANALOG | -15 | 15 | V | Full; V+ = 15 V, V- = -15 V unless specified | 2 | |
| On-Resistance | RON | 3.8 | 5.3 | Ω | Room; IS = -10 mA, VD = -10 V to +10 V | 2 | |
| On-Resistance | RON | 8.3 | Ω | Full; IS = -10 mA, VD = -10 V to +10 V | 2 | ||
| On-Resistance Match | ΔRON | 0.12 | 0.5 | Ω | Room; IS = -10 mA, VD = ±10 V | 2 | |
| On-Resistance Match | ΔRON | 1 | Ω | Full; IS = -10 mA, VD = ±10 V | 2 | ||
| On-Resistance Flatness | RFLATNESS | 0.25 | 0.5 | Ω | Room; IS = -10 mA, VD = -5 V, 0 V, +5 V | 2 | |
| On-Resistance Flatness | RFLATNESS | 0.5 | Ω | Full; IS = -10 mA, VD = -5 V, 0 V, +5 V | 2 | ||
| Switch Off Leakage Current | IS(off) | -0.5 | 0.1 | 0.5 | nA | Room; VD = ±10 V, VS = 10 V | 2 |
| Switch Off Leakage Current | IS(off) | -20 | 20 | nA | Full; VD = ±10 V, VS = 10 V | 2 | |
| Channel On Leakage Current | ID(on) | -0.4 | 0.1 | 0.4 | nA | Room; VS = VD = ±10 V | 2 |
| Channel On Leakage Current | ID(on) | -40 | 40 | nA | Full; VS = VD = ±10 V | 2 | |
| Input Current, VIN Low | IIL | -0.5 | 0.005 | 0.5 | µA | Full; VIN under test = 0.8 V | 3 |
| Input Current, VIN High | IIH | -0.5 | 0.005 | 0.5 | µA | Full; VIN under test = 2.4 V | 3 |
| Turn-On Time | tON | 88 | 118 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = ±10 V | 3 | |
| Turn-On Time | tON | 160 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = ±10 V | 3 | ||
| Turn-Off Time | tOFF | 69 | 97 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = ±10 V | 3 | |
| Turn-Off Time | tOFF | 120 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = ±10 V | 3 | ||
| Power Supply Current | I+ | 0.001 | 0.5 | µA | Room; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 | |
| Power Supply Current | I+ | 5 | µA | Full; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 | ||
| Negative Supply Current | I- | -0.5 | -0.001 | µA | Room; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 | |
| Negative Supply Current | I- | -5 | µA | Full; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 | ||
| Logic Supply Current | IL | 0.001 | 0.5 | µA | Room; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 | |
| Logic Supply Current | IL | 5 | µA | Full; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 | ||
| Ground Current | IGND | -0.5 | -0.001 | µA | Room; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 | |
| Ground Current | IGND | -5 | µA | Full; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 | ||
| On-Resistance | RON | 3.8 | 11 | Ω | Room; V+ = 5 V, V- = -5 V, IS = -10 mA, VD = -3.5 V to +3.5 V | 3 | |
| On-Resistance | RON | 15 | Ω | Full; V+ = 5 V, V- = -5 V, IS = -10 mA, VD = -3.5 V to +3.5 V | 3 | ||
| On-Resistance Match | ΔRON | 0.13 | 0.5 | Ω | Room; V+ = 5 V, V- = -5 V, IS = -10 mA, VD = ±3.5 V | 3 | |
| On-Resistance Match | ΔRON | 1 | Ω | Full; V+ = 5 V, V- = -5 V, IS = -10 mA, VD = ±3.5 V | 3 | ||
| Turn-On Time | tON | 170 | 200 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = 3 V | 3 | |
| Turn-On Time | tON | 296 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = 3 V | 3 | ||
| Turn-Off Time | tOFF | 66 | 96 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = 3 V | 3 | |
| Turn-Off Time | tOFF | 124 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = 3 V | 3 | ||
| Power Supply Current | I+ | -0.5 | 0.001 | µA | Room; VL = 5 V, VIN = 0 or 5 V | 4 | |
| Power Supply Current | I+ | -5 | µA | Full; VL = 5 V, VIN = 0 or 5 V | 4 | ||
| Negative Supply Current | I- | -0.5 | -0.001 | µA | Room; VL = 5 V, VIN = 0 or 5 V | 4 | |
| Negative Supply Current | I- | -5 | µA | Full; VL = 5 V, VIN = 0 or 5 V | 4 | ||
| On-Resistance | RON | 5.5 | 8.1 | Ω | Room; V+ = 12 V, V- = 0 V, IS = -10 mA, VD = 0 V to +10 V | 4 | |
| On-Resistance | RON | 12.4 | Ω | Full; V+ = 12 V, V- = 0 V, IS = -10 mA, VD = 0 V to +10 V | 4 | ||
| On-Resistance Match | ΔRON | 0.14 | 0.5 | Ω | Room; V+ = 12 V, V- = 0 V, IS = -10 mA, VD = +10 V | 4 | |
| On-Resistance Flatness | RFLATNESS | 0.94 | 1.5 | Ω | Room; V+ = 12 V, V- = 0 V, IS = -10 mA, VD = 0 V, +5 V, +10 V | 4 | |
| On-Resistance Flatness | RFLATNESS | 1.7 | Ω | Full; V+ = 12 V, V- = 0 V, IS = -10 mA, VD = 0 V, +5 V, +10 V | 4 | ||
| Turn-On Time | tON | 132 | 162 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = 8 V | 4 | |
| Turn-On Time | tON | 238 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = 8 V | 4 | ||
| Turn-Off Time | tOFF | 61 | 91 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = 8 V | 4 | |
| Turn-Off Time | tOFF | 117 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = 8 V | 4 | ||
| Power Supply Current | I+ | 0.001 | 0.5 | µA | Room; VL = 5 V, VIN = 0 or 5 V | 4 | |
| Power Supply Current | I+ | 5 | µA | Full; VL = 5 V, VIN = 0 or 5 V | 4 | ||
| V+ to V- | 44 | V | 2 | ||||
| GND to V- | 25 | V | 2 | ||||
| Continuous Current (D, S only) | 100 | mA | 2 | ||||
| Peak Current, S or D | 300 | Pulsed 1 ms, 10 % Duty Cycle | 2 | ||||
| Storage Temperature | -65 | 150 | °C | 2 | |||
| Power Dissipation (Package), 16 Pin TSSOP | 450 | mW | Derate 5.6 mW/°C above 70 °C | 2 | |||
| Operating Temperature Range (EQ grade, 16 Pin TSSOP) | -40 | 125 | °C | Ordering part DG453EQ-T1-E3 | 2 | ||
| Thermal Resistance (Package), 16 Pin TSSOP | 178 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
DG453EQ-T1-E3 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dg453eq-t1-e3-etched.step/dg453eq-t1-e3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dg453eq-t1-e3.step/dg453eq-t1-e3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (13 pp, sha256
c81e44d110818cf6, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DG453EQ-T1-E3
**Vishay Intertech** · Analog Switches, Multiplexers · TSSOP-16
DG453EQ-T1-E3 from Vishay Intertech, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN1 | input | Digital logic control input for switch S1/D1; TTL/CMOS compatible with 0.8 V and 2.4 V logic thresholds. |
| 2 | D1 | passive | Drain terminal of switch 1; the signal range extends to the supply voltage rails and signals exceeding V+ or V- are clamped by internal diodes. |
| 3 | S1 | passive | Source terminal of switch 1; the analog signal range is ±15 V with dual supplies and the switch conducts equally well in both directions when on. |
| 4 | V- | power_in | Negative analog supply; V+ to V- is rated at 44 V maximum and GND to V- at 25 V maximum. |
| 5 | GND | power_in | Ground reference for the device; GND to V- is rated at 25 V maximum. |
| 6 | S4 | passive | Source terminal of switch 4; the analog signal range is ±15 V with dual supplies and the switch conducts equally well in both directions when on. |
| 7 | D4 | passive | Drain terminal of switch 4; the signal range extends to the supply voltage rails and signals exceeding V+ or V- are clamped by internal diodes. |
| 8 | IN4 | input | Digital logic control input for switch S4/D4; TTL/CMOS compatible with 0.8 V and 2.4 V logic thresholds. |
| 9 | IN3 | input | Digital logic control input for switch S3/D3; TTL/CMOS compatible with 0.8 V and 2.4 V logic thresholds. |
| 10 | D3 | passive | Drain terminal of switch 3; the signal range extends to the supply voltage rails and signals exceeding V+ or V- are clamped by internal diodes. |
| 11 | S3 | passive | Source terminal of switch 3; the analog signal range is ±15 V with dual supplies and the switch conducts equally well in both directions when on. |
| 12 | VL | power_in | Logic supply; per the absolute maximum ratings VL must be kept between (GND - 0.3) V and (V+) + 0.3 V, and the datasheet tests use VL = 5 V. |
| 13 | V+ | power_in | Positive analog supply; V+ to V- is rated at 44 V maximum. |
| 14 | S2 | passive | Source terminal of switch 2; the analog signal range is ±15 V with dual supplies and the switch conducts equally well in both directions when on. |
| 15 | D2 | passive | Drain terminal of switch 2; the signal range extends to the supply voltage rails and signals exceeding V+ or V- are clamped by internal diodes. |
| 16 | IN2 | input | Digital logic control input for switch S2/D2; TTL/CMOS compatible with 0.8 V and 2.4 V logic thresholds. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Signal Range | VANALOG | -15 | | 15 | V | Full; V+ = 15 V, V- = -15 V unless specified | 2 |
| On-Resistance | RON | | 3.8 | 5.3 | Ω | Room; IS = -10 mA, VD = -10 V to +10 V | 2 |
| On-Resistance | RON | | | 8.3 | Ω | Full; IS = -10 mA, VD = -10 V to +10 V | 2 |
| On-Resistance Match | ΔRON | | 0.12 | 0.5 | Ω | Room; IS = -10 mA, VD = ±10 V | 2 |
| On-Resistance Match | ΔRON | | | 1 | Ω | Full; IS = -10 mA, VD = ±10 V | 2 |
| On-Resistance Flatness | RFLATNESS | | 0.25 | 0.5 | Ω | Room; IS = -10 mA, VD = -5 V, 0 V, +5 V | 2 |
| On-Resistance Flatness | RFLATNESS | | | 0.5 | Ω | Full; IS = -10 mA, VD = -5 V, 0 V, +5 V | 2 |
| Switch Off Leakage Current | IS(off) | -0.5 | 0.1 | 0.5 | nA | Room; VD = ±10 V, VS = 10 V | 2 |
| Switch Off Leakage Current | IS(off) | -20 | | 20 | nA | Full; VD = ±10 V, VS = 10 V | 2 |
| Channel On Leakage Current | ID(on) | -0.4 | 0.1 | 0.4 | nA | Room; VS = VD = ±10 V | 2 |
| Channel On Leakage Current | ID(on) | -40 | | 40 | nA | Full; VS = VD = ±10 V | 2 |
| Input Current, VIN Low | IIL | -0.5 | 0.005 | 0.5 | µA | Full; VIN under test = 0.8 V | 3 |
| Input Current, VIN High | IIH | -0.5 | 0.005 | 0.5 | µA | Full; VIN under test = 2.4 V | 3 |
| Turn-On Time | tON | | 88 | 118 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = ±10 V | 3 |
| Turn-On Time | tON | | | 160 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = ±10 V | 3 |
| Turn-Off Time | tOFF | | 69 | 97 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = ±10 V | 3 |
| Turn-Off Time | tOFF | | | 120 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = ±10 V | 3 |
| Power Supply Current | I+ | | 0.001 | 0.5 | µA | Room; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 |
| Power Supply Current | I+ | | | 5 | µA | Full; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 |
| Negative Supply Current | I- | -0.5 | -0.001 | | µA | Room; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 |
| Negative Supply Current | I- | -5 | | | µA | Full; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 |
| Logic Supply Current | IL | | 0.001 | 0.5 | µA | Room; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 |
| Logic Supply Current | IL | | | 5 | µA | Full; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 |
| Ground Current | IGND | -0.5 | -0.001 | | µA | Room; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 |
| Ground Current | IGND | -5 | | | µA | Full; V+ = 16.5 V, V- = -16.5 V, VL = 5 V, VIN = 0 or 5 V | 3 |
| On-Resistance | RON | | 3.8 | 11 | Ω | Room; V+ = 5 V, V- = -5 V, IS = -10 mA, VD = -3.5 V to +3.5 V | 3 |
| On-Resistance | RON | | | 15 | Ω | Full; V+ = 5 V, V- = -5 V, IS = -10 mA, VD = -3.5 V to +3.5 V | 3 |
| On-Resistance Match | ΔRON | | 0.13 | 0.5 | Ω | Room; V+ = 5 V, V- = -5 V, IS = -10 mA, VD = ±3.5 V | 3 |
| On-Resistance Match | ΔRON | | | 1 | Ω | Full; V+ = 5 V, V- = -5 V, IS = -10 mA, VD = ±3.5 V | 3 |
| Turn-On Time | tON | | 170 | 200 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = 3 V | 3 |
| Turn-On Time | tON | | | 296 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = 3 V | 3 |
| Turn-Off Time | tOFF | | 66 | 96 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = 3 V | 3 |
| Turn-Off Time | tOFF | | | 124 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = 3 V | 3 |
| Power Supply Current | I+ | -0.5 | 0.001 | | µA | Room; VL = 5 V, VIN = 0 or 5 V | 4 |
| Power Supply Current | I+ | -5 | | | µA | Full; VL = 5 V, VIN = 0 or 5 V | 4 |
| Negative Supply Current | I- | -0.5 | -0.001 | | µA | Room; VL = 5 V, VIN = 0 or 5 V | 4 |
| Negative Supply Current | I- | -5 | | | µA | Full; VL = 5 V, VIN = 0 or 5 V | 4 |
| On-Resistance | RON | | 5.5 | 8.1 | Ω | Room; V+ = 12 V, V- = 0 V, IS = -10 mA, VD = 0 V to +10 V | 4 |
| On-Resistance | RON | | | 12.4 | Ω | Full; V+ = 12 V, V- = 0 V, IS = -10 mA, VD = 0 V to +10 V | 4 |
| On-Resistance Match | ΔRON | | 0.14 | 0.5 | Ω | Room; V+ = 12 V, V- = 0 V, IS = -10 mA, VD = +10 V | 4 |
| On-Resistance Flatness | RFLATNESS | | 0.94 | 1.5 | Ω | Room; V+ = 12 V, V- = 0 V, IS = -10 mA, VD = 0 V, +5 V, +10 V | 4 |
| On-Resistance Flatness | RFLATNESS | | | 1.7 | Ω | Full; V+ = 12 V, V- = 0 V, IS = -10 mA, VD = 0 V, +5 V, +10 V | 4 |
| Turn-On Time | tON | | 132 | 162 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = 8 V | 4 |
| Turn-On Time | tON | | | 238 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = 8 V | 4 |
| Turn-Off Time | tOFF | | 61 | 91 | ns | Room; RL = 300 Ω, CL = 35 pF, VS = 8 V | 4 |
| Turn-Off Time | tOFF | | | 117 | ns | Full; RL = 300 Ω, CL = 35 pF, VS = 8 V | 4 |
| Power Supply Current | I+ | | 0.001 | 0.5 | µA | Room; VL = 5 V, VIN = 0 or 5 V | 4 |
| Power Supply Current | I+ | | | 5 | µA | Full; VL = 5 V, VIN = 0 or 5 V | 4 |
| V+ to V- | | | | 44 | V | | 2 |
| GND to V- | | | | 25 | V | | 2 |
| Continuous Current (D, S only) | | | | 100 | mA | | 2 |
| Peak Current, S or D | | | | 300 | | Pulsed 1 ms, 10 % Duty Cycle | 2 |
| Storage Temperature | | -65 | | 150 | °C | | 2 |
| Power Dissipation (Package), 16 Pin TSSOP | | | | 450 | mW | Derate 5.6 mW/°C above 70 °C | 2 |
| Operating Temperature Range (EQ grade, 16 Pin TSSOP) | | -40 | | 125 | °C | Ordering part DG453EQ-T1-E3 | 2 |
| Thermal Resistance (Package), 16 Pin TSSOP | | | 178 | | °C/W | | 2 |
## CAD (KiCad official)
- Symbol: `DG453EQ-T1-E3`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `dg453eq-t1-e3-etched.step` / `dg453eq-t1-e3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dg453eq-t1-e3.step` / `dg453eq-t1-e3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588938074655240192) (13 pp, sha256 `c81e44d110818cf6`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dg453eq-t1-e3-datasheet.pdf)