component

DG444DY-T1-E3

Public Made by Adom

by adom

Vishay Analog Switches, Multiplexers, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs dg444dy-t1-e3: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers dg444dy-t1-e3: viewers · Ray
dg444dy-t1-e3-etched.fit.json dg444dy-t1-e3: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dg444dy-t1-e3-etched.glb dg444dy-t1-e3: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dg444dy-t1-e3-etched.step dg444dy-t1-e3: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dg444dy-t1-e3.glb Publish 0.1.0 · Ray
dg444dy-t1-e3.kicad_mod Publish 0.1.0 · Ray
dg444dy-t1-e3.kicad_sym Publish 0.1.0 · Ray
dg444dy-t1-e3.lbr Publish 0.1.0 · Ray
dg444dy-t1-e3.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
page.json dg444dy-t1-e3: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md dg444dy-t1-e3: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

DG444DY-T1-E3

Vishay · Analog Switches, Multiplexers · SOIC-16

DG444DY-T1-E3 from Vishay, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1 input Digital control input for switch 1. TTL/CMOS compatible: logic '0' ≤ 0.8 V (switch on for DG444), logic '1' ≥ 2.4 V (switch off for DG444).
2 D1 passive Drain terminal of analog switch 1. Bidirectional analog signal path; conducts equally in both directions when on. Analog signal range ±15 V (dual supply).
3 S1 passive Source terminal of analog switch 1. Bidirectional analog signal path paired with D1 through the switch (RDS(on) ≈ 50 Ω typ).
4 V- power_in Negative analog supply. Dual-supply operation -5 V to -20 V (typ -15 V); tie to GND for single-supply operation. Absolute max V+ to V- = 44 V; GND to V- = 25 V.
5 GND power_in Ground / analog reference.
6 S4 passive Source terminal of analog switch 4. Bidirectional analog signal path paired with D4.
7 D4 passive Drain terminal of analog switch 4. Bidirectional analog signal path.
8 IN4 input Digital control input for switch 4. TTL/CMOS compatible: logic '0' ≤ 0.8 V, logic '1' ≥ 2.4 V.
9 IN3 input Digital control input for switch 3. TTL/CMOS compatible: logic '0' ≤ 0.8 V, logic '1' ≥ 2.4 V.
10 D3 passive Drain terminal of analog switch 3. Bidirectional analog signal path.
11 S3 passive Source terminal of analog switch 3. Bidirectional analog signal path paired with D3.
12 VL power_in Logic supply voltage. Sets logic threshold; typical +5 V. Range (GND - 0.3 V) to (V+ + 0.3 V) absolute max.
13 V+ power_in Positive analog supply. Single-supply +5 V to +36 V, or dual-supply +5 V to +20 V (typ +15 V). V+ to V- absolute max = 44 V.
14 S2 passive Source terminal of analog switch 2. Bidirectional analog signal path paired with D2.
15 D2 passive Drain terminal of analog switch 2. Bidirectional analog signal path.
16 IN2 input Digital control input for switch 2. TTL/CMOS compatible: logic '0' ≤ 0.8 V, logic '1' ≥ 2.4 V.

Key specifications

Parameter Value
Manufacturer Vishay
Package SOIC-16
Category Interface
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • DG444DY-T1-E3
  • DG444DY-T1-E3DJ

CAD (KiCad official)

  • Symbol: DG444DY-T1-E3
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: dg444dy-t1-e3-etched.step / dg444dy-t1-e3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dg444dy-t1-e3.step / dg444dy-t1-e3.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
dg444dy-t1-e3.step 217 KB You want the bare part, or you mark your own boards.
dg444dy-t1-e3-etched.step 2.3 MB You want the part with DG444DY-T1-E3 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 617 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay datasheet (12 pp, sha256 b9eeefb3fe45570b, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF