component
DG419DY-T1-E3
Public Made by Adomby adom
Vishay Analog Switches, Multiplexers, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
dg419dy-t1-e3: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
b7e065b
17h ago
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{
"schema_version": 1,
"type": "component",
"slug": "dg419dy-t1-e3",
"title": "DG419DY-T1-E3",
"brief": "Vishay Analog Switches, Multiplexers, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.2.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"interface",
"dg419dy-t1-e3"
],
"component": {
"mpn": "DG419DY-T1-E3",
"manufacturer": "Vishay",
"package": "SOIC-8",
"pin_count": 8,
"category": "Interface",
"subcategory": "Analog Switches, Multiplexers",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/f1528dc32df34dc880d26d52f5c1d07a.pdf",
"parts": {
"symbol": "dg419dy-t1-e3.kicad_sym",
"footprint": "dg419dy-t1-e3.kicad_mod",
"model_3d": "dg419dy-t1-e3-etched.glb",
"model_3d_plain": "dg419dy-t1-e3.glb",
"model_3d_step": "dg419dy-t1-e3-etched.step",
"model_3d_step_plain": "dg419dy-t1-e3.step",
"lbr": "dg419dy-t1-e3.lbr"
},
"distributor_links": {
"lcsc": "C6581"
},
"pins": [
{
"number": "1",
"name": "D",
"type": "passive",
"description": "Drain (common terminal). Analog I/O common to both SPDT throws (S1 and S2). Bidirectional analog path; blocks up to the supply rail when the corresponding switch is off. Signal range ±15 V (bipolar) or 0-12 V (unipolar)."
},
{
"number": "2",
"name": "S1",
"type": "passive",
"description": "Source 1 (SPDT throw 1). Bidirectional analog terminal; connected to D when IN = logic 0 (SW1 ON). rDS(on) ≈ 20 Ω typical at V+/V- = ±15 V."
},
{
"number": "3",
"name": "GND",
"type": "power_in",
"description": "Ground reference for the digital control input. Referenced to VL for logic thresholds (VIL ≤ 0.8 V, VIH ≥ 2.4 V)."
},
{
"number": "4",
"name": "V+",
"type": "power_in",
"description": "Positive analog supply. Operating range up to +15 V for bipolar operation, or up to +12 V unipolar (with V- = 0 V). Absolute maximum V+ referenced to V- is 44 V."
},
{
"number": "5",
"name": "VL",
"type": "power_in",
"description": "Logic supply. Sets the input switching threshold for the IN pin (typ. VL = 5 V for TTL/CMOS compatibility). Range (GND - 0.3) to (V+) + 0.3 V."
},
{
"number": "6",
"name": "IN",
"type": "input",
"description": "Digital control input, TTL/CMOS compatible. Logic 0 (≤ 0.8 V): SW1 ON, SW2 OFF. Logic 1 (≥ 2.4 V): SW1 OFF, SW2 ON. Input current typ. 5 nA."
},
{
"number": "7",
"name": "V-",
"type": "power_in",
"description": "Negative analog supply. Typically -15 V for bipolar operation; tie to GND for unipolar (single-supply) operation. Absolute maximum V+ - V- ≤ 44 V."
},
{
"number": "8",
"name": "S2",
"type": "passive",
"description": "Source 2 (SPDT throw 2). Bidirectional analog terminal; connected to D when IN = logic 1 (SW2 ON). Break-before-make guaranteed with S1 (tD ≈ 13 ns typ.)."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/f1528dc32df34dc880d26d52f5c1d07a.pdf",
"pages": 11,
"sha256": "32ddbc30ce7ed19a",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"pin1": {
"pad": "1",
"at": [
-2.475,
-1.905
],
"corner": "top-left",
"source": "silk-marker",
"derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
"mark": "drawn"
},
"models_3d": [
{
"file": "dg419dy-t1-e3.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
4.9,
1.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "dg419dy-t1-e3-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
4.9,
1.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "de25453e646486b44cffbdb7a192dc6065e108a4217569277425e1c7b8db469a",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Vishay",
"Package": "SOIC-8",
"Category": "Interface",
"Pins": "8"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"dg419dy-t1-e3"
],
"discovery_pitch": "DG419DY-T1-E3 (Vishay) component page with datasheet-verified CAD.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"dg419dy-t1-e3.kicad_sym",
"dg419dy-t1-e3.kicad_mod",
"dg419dy-t1-e3.glb",
"dg419dy-t1-e3.step",
"dg419dy-t1-e3-etched.step",
"dg419dy-t1-e3.lbr",
"docs/hero.png",
"docs/dg419dy-t1-e3-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html"
],
"visibility": {
"public": true
},
"variants": [
{
"mpn": "DG419DY-T1-E3",
"kind": "packaging"
},
{
"mpn": "DG419DY-T1-E3DY-E3",
"kind": "packaging"
},
{
"mpn": "DG419DY-T1-E3DJ",
"kind": "packaging"
},
{
"mpn": "DG419DY-T1-E3DJ-E3",
"kind": "packaging"
}
],
"updated_at": "2026-09-24T19:44:45.624Z"
}