component
DG409DQ-T1-E3
Public Made by Adomby adom
Vishay Intertech Analog Switches, Multiplexers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownDG409DQ-T1-E3
Vishay Intertech · Analog Switches, Multiplexers · TSSOP-16
DG409DQ-T1-E3 from Vishay Intertech, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Address bit 0 (LSB) of the 2-bit binary address selecting one of four differential channels; TTL compatible, logic 0 ≤ 0.8 V and logic 1 ≥ 2.4 V. |
| 2 | EN | input | Enable input; logic 0 turns all switches off, logic 1 enables the addressed channel; TTL compatible (0.8 V / 2.4 V thresholds). |
| 3 | V- | power_in | Negative supply; dual supplies are ±5 V to ±20 V, V+ to V- max 44 V, and it can be tied to GND for single-supply operation. |
| 4 | S1a | bidirectional | Source/input 1 of channel group a; conducts equally in both directions and blocks voltages up to the supply rails when off. |
| 5 | S2a | bidirectional | Source/input 2 of channel group a; conducts equally in both directions and blocks voltages up to the supply rails when off. |
| 6 | S3a | bidirectional | Source/input 3 of channel group a; conducts equally in both directions and blocks voltages up to the supply rails when off. |
| 7 | S4a | bidirectional | Source/input 4 of channel group a; conducts equally in both directions and blocks voltages up to the supply rails when off. |
| 8 | Da | bidirectional | Common drain/output of channel group a (S1a-S4a); signals beyond V+ or V- are clamped by internal diodes, so limit current to 30 mA. |
| 9 | Db | bidirectional | Common drain/output of channel group b (S1b-S4b); signals beyond V+ or V- are clamped by internal diodes, so limit current to 30 mA. |
| 10 | S4b | bidirectional | Source/input 4 of channel group b; conducts equally in both directions and blocks voltages up to the supply rails when off. |
| 11 | S3b | bidirectional | Source/input 3 of channel group b; conducts equally in both directions and blocks voltages up to the supply rails when off. |
| 12 | S2b | bidirectional | Source/input 2 of channel group b; conducts equally in both directions and blocks voltages up to the supply rails when off. |
| 13 | S1b | bidirectional | Source/input 1 of channel group b; conducts equally in both directions and blocks voltages up to the supply rails when off. |
| 14 | V+ | power_in | Positive supply; single supply +5 V to 36 V, dual supplies ±5 V to ±20 V, V+ to V- max 44 V. |
| 15 | GND | power_in | Ground reference for the logic inputs; GND to V- must not exceed 25 V (abs max). |
| 16 | A1 | input | Address bit 1 (MSB) of the 2-bit binary address selecting one of four differential channels; TTL compatible, logic 0 ≤ 0.8 V and logic 1 ≥ 2.4 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Signal Range | VANALOG | -15 | 15 | V | 3 | ||
| Drain-Source On-Resistance (Room) | RDS(on) | 40 | 100 | Ω | VD = ± 10 V, IS = -10 mA | 3 | |
| Drain-Source On-Resistance (Full, -40 °C to 85 °C) | RDS(on) | 125 | Ω | VD = ± 10 V, IS = -10 mA | 3 | ||
| RDS(on) Matching Between Channels (Room) | RDS(on) | 15 | Ω | VD = ± 10 V | 3 | ||
| Source Off Leakage Current (Room) | IS(off) | -0.5 | 0.5 | nA | VS = ± 10 V, VD = ± 10 V, VEN = 0 V | 3 | |
| Source Off Leakage Current (Full) | IS(off) | -5 | 5 | nA | VS = ± 10 V, VD = ± 10 V, VEN = 0 V | 3 | |
| Drain Off Leakage Current DG409 (Room) | ID(off) | -1 | 1 | nA | VD = ± 10 V, VS = ± 10 V, VEN = 0 V | 3 | |
| Drain Off Leakage Current DG409 (Full) | ID(off) | -10 | 10 | nA | VD = ± 10 V, VS = ± 10 V, VEN = 0 V | 3 | |
| Drain On Leakage Current DG409 (Room) | ID(on) | -1 | 1 | nA | VS = VD = ± 10 V sequence each switch on | 3 | |
| Drain On Leakage Current DG409 (Full) | ID(on) | -10 | 10 | nA | VS = VD = ± 10 V sequence each switch on | 3 | |
| Logic High Input Voltage (Full) | VINH | 2.4 | V | 3 | |||
| Logic Low Input Voltage (Full) | VINL | 0.8 | V | 3 | |||
| Logic High Input Current (Full) | IAH | -10 | 10 | μA | VA = 2.4 V, 15 V | 3 | |
| Logic Low Input Current (Full) | IAL | -10 | 10 | μA | VEN = 0 V, 2.4 V, VA = 0 V | 3 | |
| Transition Time (Full) | tTRANS | 160 | 250 | ns | see figure 2 | 3 | |
| Break-Before-Make Interval (Room) | tOPEN | 10 | ns | see figure 4 | 3 | ||
| Enable Turn-On Time (Room) | tON(EN) | 115 | 150 | ns | see figure 3 | 3 | |
| Enable Turn-Off Time (Room) | tOFF(EN) | 105 | 150 | ns | see figure 3 | 3 | |
| Positive Supply Current (Full) | I+ | 10 | 75 | μA | VEN = VA = 0 V or 5 V | 3 | |
| Negative Supply Current (Full) | I- | -75 | 1 | μA | 3 | ||
| Positive Supply Current (Room) | I+ | 0.2 | 0.5 | mA | VEN = VA = 0 V or 5 V | 3 | |
| Positive Supply Current (Full) | I+ | 2 | mA | VEN = VA = 0 V or 5 V | 3 | ||
| Negative Supply Current (Full) | I- | -500 | μA | 3 | |||
| V+ to V- Voltage | 44 | V | 2 | ||||
| GND to V- Voltage | -25 | V | 2 | ||||
| Current (any terminal) | 30 | mA | 2 | ||||
| Peak Current S or D | 100 | mA | pulsed at 1 ms, 10 % duty cycle max. | 2 | |||
| Storage Temperature (DQ/DY/DJ suffix) | -65 | 125 | °C | 2 | |||
| Power Dissipation (Package) 16-pin narrow SOIC and TSSOP | 600 | mW | 16-pin narrow SOIC and TSSOP; derate 7.6 mW/°C above 75 °C (note d) | 2 | |||
| Single Supply Voltage (V+ to V-) | 5 | 36 | V | Single supply | 1 | ||
| Dual Supply Voltage magnitude (±) | 5 | 20 | V | Dual supplies ±5 V to ±20 V | 1 | ||
| Operating Temperature Range (D suffix) | -40 | 85 | °C | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | • -T1 indicates Tape and Reel, -E3 indicates Lead-Free and RoHS Compliant, NO -E3 indicates standard Tin/Lead finish. Notes | 2 |
CAD (KiCad official)
- Symbol:
DG409DQ-T1-E3 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dg409dq-t1-e3-etched.step/dg409dq-t1-e3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dg409dq-t1-e3.step/dg409dq-t1-e3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (17 pp, sha256
950673efec0223bf, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).