component
DG4053EEQ-T1-GE3
Public Made by Adomby adom
VISHAY Global Sourcing Parts, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DG4053EEQ-T1-GE3
VISHAY · Global Sourcing Parts · TSSOP-16
DG4053EEQ-T1-GE3 from VISHAY, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | bidirectional | Y switch channel 1 terminal, selected when B is high; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 2 | Y0 | bidirectional | Y switch channel 0 terminal, selected when B is low; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 3 | Z1 | bidirectional | Z switch channel 1 terminal, selected when C is high; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 4 | Z | bidirectional | Z common terminal of the Z SPDT switch, which conducts in both directions with rail-to-rail analog signal range. |
| 5 | Z0 | bidirectional | Z switch channel 0 terminal, selected when C is low; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 6 | ENABLE | input | Enable logic input; low lets the address pins control the switches and high turns all switches off, with a guaranteed 2 V logic high limit at 5 V or ±5 V supplies and 1.4 V at a 3 V supply. |
| 7 | V- | power_in | Negative supply, used in dual-supply operation of ±3 V to ±8 V (tied to ground for single supply), with V+ to V- rated -0.3 V to +18 V. |
| 8 | GND | power_in | Ground reference for the logic, with GND to V- rated at -18 V maximum. |
| 9 | C | input | Address input selecting Z0 or Z1 for the Z switch, with a guaranteed 2 V logic high limit at 5 V or ±5 V supplies and 1.4 V at a 3 V supply. |
| 10 | B | input | Address input selecting Y0 or Y1 for the Y switch, with a guaranteed 2 V logic high limit at 5 V or ±5 V supplies and 1.4 V at a 3 V supply. |
| 11 | A | input | Address input selecting X0 or X1 for the X switch, with a guaranteed 2 V logic high limit at 5 V or ±5 V supplies and 1.4 V at a 3 V supply. |
| 12 | X0 | bidirectional | X switch channel 0 terminal, selected when A is low; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 13 | X1 | bidirectional | X switch channel 1 terminal, selected when A is high; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 14 | X | bidirectional | X common terminal of the X SPDT switch, which conducts in both directions with rail-to-rail analog signal range. |
| 15 | Y | bidirectional | Y common terminal of the Y SPDT switch, which conducts in both directions with rail-to-rail analog signal range. |
| 16 | V+ | power_in | Positive supply, 3 V to 16 V single supply or up to ±8 V dual supply, with V+ to V- rated -0.3 V to +18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VISHAY |
| Package | TSSOP-16 |
| Category | Global Sourcing Parts |
| Pins | 16 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | f. Manual soldering with iron is not recommended for leadless components. The miniQFN-16 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulati | 3 |
CAD (KiCad official)
- Symbol:
DG4053EEQ-T1-GE3 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dg4053eeq-t1-ge3-etched.step/dg4053eeq-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dg4053eeq-t1-ge3.step/dg4053eeq-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VISHAY datasheet (21 pp, sha256
d889a777c81f98ad, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DG4053EEQ-T1-GE3
**VISHAY** · Global Sourcing Parts · TSSOP-16
DG4053EEQ-T1-GE3 from VISHAY, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | bidirectional | Y switch channel 1 terminal, selected when B is high; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 2 | Y0 | bidirectional | Y switch channel 0 terminal, selected when B is low; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 3 | Z1 | bidirectional | Z switch channel 1 terminal, selected when C is high; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 4 | Z | bidirectional | Z common terminal of the Z SPDT switch, which conducts in both directions with rail-to-rail analog signal range. |
| 5 | Z0 | bidirectional | Z switch channel 0 terminal, selected when C is low; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 6 | ENABLE | input | Enable logic input; low lets the address pins control the switches and high turns all switches off, with a guaranteed 2 V logic high limit at 5 V or ±5 V supplies and 1.4 V at a 3 V supply. |
| 7 | V- | power_in | Negative supply, used in dual-supply operation of ±3 V to ±8 V (tied to ground for single supply), with V+ to V- rated -0.3 V to +18 V. |
| 8 | GND | power_in | Ground reference for the logic, with GND to V- rated at -18 V maximum. |
| 9 | C | input | Address input selecting Z0 or Z1 for the Z switch, with a guaranteed 2 V logic high limit at 5 V or ±5 V supplies and 1.4 V at a 3 V supply. |
| 10 | B | input | Address input selecting Y0 or Y1 for the Y switch, with a guaranteed 2 V logic high limit at 5 V or ±5 V supplies and 1.4 V at a 3 V supply. |
| 11 | A | input | Address input selecting X0 or X1 for the X switch, with a guaranteed 2 V logic high limit at 5 V or ±5 V supplies and 1.4 V at a 3 V supply. |
| 12 | X0 | bidirectional | X switch channel 0 terminal, selected when A is low; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 13 | X1 | bidirectional | X switch channel 1 terminal, selected when A is high; the signal is clamped by internal diodes if it exceeds V+ or V-, and must stay within (V-) - 0.3 V to (V+) + 0.3 V. |
| 14 | X | bidirectional | X common terminal of the X SPDT switch, which conducts in both directions with rail-to-rail analog signal range. |
| 15 | Y | bidirectional | Y common terminal of the Y SPDT switch, which conducts in both directions with rail-to-rail analog signal range. |
| 16 | V+ | power_in | Positive supply, 3 V to 16 V single supply or up to ±8 V dual supply, with V+ to V- rated -0.3 V to +18 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VISHAY |
| Package | TSSOP-16 |
| Category | Global Sourcing Parts |
| Pins | 16 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | f. Manual soldering with iron is not recommended for leadless components. The miniQFN-16 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulati | 3 |
## CAD (KiCad official)
- Symbol: `DG4053EEQ-T1-GE3`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `dg4053eeq-t1-ge3-etched.step` / `dg4053eeq-t1-ge3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dg4053eeq-t1-ge3.step` / `dg4053eeq-t1-ge3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [VISHAY datasheet](docs/dg4053eeq-t1-ge3-datasheet.pdf) (21 pp, sha256 `d889a777c81f98ad`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dg4053eeq-t1-ge3-datasheet.pdf)