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DG403DY-T1-E3
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Vishay Intertech Analog Switches, Multiplexers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DG403DY-T1-E3
Vishay Intertech · Analog Switches, Multiplexers · SOIC-16
DG403DY-T1-E3 from Vishay Intertech, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D1 | passive | Drain terminal of switch 1 (SPDT pair with S1); conducts equally well in both directions, signal range V- to V+ (±15 V). |
| 2 | NC | unconnected | No connection. |
| 3 | D3 | passive | Drain terminal of switch 3, which is ON when logic input IN1 is 0 and OFF when it is 1. |
| 4 | S3 | passive | Source terminal of switch 3, which is ON when logic input IN1 is 0 and OFF when it is 1. |
| 5 | S4 | passive | Source terminal of switch 4, which is ON when logic input IN2 is 0 and OFF when it is 1. |
| 6 | D4 | passive | Drain terminal of switch 4, which is ON when logic input IN2 is 0 and OFF when it is 1. |
| 7 | NC | unconnected | No connection. |
| 8 | D2 | passive | Drain terminal of switch 2 (SPDT pair with S2); conducts equally well in both directions. |
| 9 | S2 | passive | Source terminal of switch 2, which is ON when logic input IN2 is 1 and OFF when it is 0. |
| 10 | IN2 | input | Logic control input for switches 2 and 4 (logic 0 ≤ 0.8 V, logic 1 ≥ 2.4 V). |
| 11 | V+ | power_in | Positive supply voltage; V+ to V- is rated 44 V maximum. |
| 12 | VL | power_in | Logic supply; absolute maximum is (GND - 0.3) V to (V+) + 0.3 V. |
| 13 | GND | power_in | Ground; GND to V- is rated 25 V maximum. |
| 14 | V- | power_in | Negative supply voltage; V+ to V- is rated 44 V maximum. |
| 15 | IN1 | input | Logic control input for switches 1 and 3 (logic 0 ≤ 0.8 V, logic 1 ≥ 2.4 V). |
| 16 | S1 | passive | Source terminal of switch 1, which is ON when logic input IN1 is 1 and OFF when it is 0. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SOIC-16 |
| Category | Interface |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
DG403DY-T1-E3 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
dg403dy-t1-e3-etched.step/dg403dy-t1-e3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dg403dy-t1-e3.step/dg403dy-t1-e3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (15 pp, sha256
ff3c914882a9e452, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DG403DY-T1-E3
**Vishay Intertech** · Analog Switches, Multiplexers · SOIC-16
DG403DY-T1-E3 from Vishay Intertech, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D1 | passive | Drain terminal of switch 1 (SPDT pair with S1); conducts equally well in both directions, signal range V- to V+ (±15 V). |
| 2 | NC | unconnected | No connection. |
| 3 | D3 | passive | Drain terminal of switch 3, which is ON when logic input IN1 is 0 and OFF when it is 1. |
| 4 | S3 | passive | Source terminal of switch 3, which is ON when logic input IN1 is 0 and OFF when it is 1. |
| 5 | S4 | passive | Source terminal of switch 4, which is ON when logic input IN2 is 0 and OFF when it is 1. |
| 6 | D4 | passive | Drain terminal of switch 4, which is ON when logic input IN2 is 0 and OFF when it is 1. |
| 7 | NC | unconnected | No connection. |
| 8 | D2 | passive | Drain terminal of switch 2 (SPDT pair with S2); conducts equally well in both directions. |
| 9 | S2 | passive | Source terminal of switch 2, which is ON when logic input IN2 is 1 and OFF when it is 0. |
| 10 | IN2 | input | Logic control input for switches 2 and 4 (logic 0 ≤ 0.8 V, logic 1 ≥ 2.4 V). |
| 11 | V+ | power_in | Positive supply voltage; V+ to V- is rated 44 V maximum. |
| 12 | VL | power_in | Logic supply; absolute maximum is (GND - 0.3) V to (V+) + 0.3 V. |
| 13 | GND | power_in | Ground; GND to V- is rated 25 V maximum. |
| 14 | V- | power_in | Negative supply voltage; V+ to V- is rated 44 V maximum. |
| 15 | IN1 | input | Logic control input for switches 1 and 3 (logic 0 ≤ 0.8 V, logic 1 ≥ 2.4 V). |
| 16 | S1 | passive | Source terminal of switch 1, which is ON when logic input IN1 is 1 and OFF when it is 0. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SOIC-16 |
| Category | Interface |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `DG403DY-T1-E3`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `dg403dy-t1-e3-etched.step` / `dg403dy-t1-e3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dg403dy-t1-e3.step` / `dg403dy-t1-e3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586193638258839552) (15 pp, sha256 `ff3c914882a9e452`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dg403dy-t1-e3-datasheet.pdf)