DG401DY-T1-E3 from Vishay Intertech, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D1	passive	Drain terminal of switch 1; the switch conducts equally in both directions when on and blocks up to 30 V peak-to-peak when off.
2	NC	unconnected	No connection.
3	NC	unconnected	No connection.
4	NC	unconnected	No connection.
5	NC	unconnected	No connection.
6	NC	unconnected	No connection.
7	NC	unconnected	No connection.
8	D2	passive	Drain terminal of switch 2; the switch conducts equally in both directions when on and blocks up to 30 V peak-to-peak when off.
9	S2	passive	Source terminal of switch 2; analog signal range is ±15 V.
10	IN2	input	Logic control input for switch 2; logic 0 is 0.8 V or less (switch OFF) and logic 1 is 2.4 V or more (switch ON).
11	V+	power_in	Positive supply voltage; V+ to V- is rated at a maximum of 44 V.
12	VL	power_in	Logic supply voltage; absolute maximum rating is (GND - 0.3) V to (V+) + 0.3 V.
13	GND	power_in	Ground; GND to V- is rated at a maximum of 25 V.
14	V-	power_in	Negative supply voltage; V+ to V- is rated at a maximum of 44 V.
15	IN1	input	Logic control input for switch 1; logic 0 is 0.8 V or less (switch OFF) and logic 1 is 2.4 V or more (switch ON).
16	S1	passive	Source terminal of switch 1; analog signal range is ±15 V.

Key specifications

Parameter	Value
Manufacturer	Vishay Intertech
Package	SOIC-16
Category	Triode/MOS Tube/Transistor
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog Signal Range	VANALOG	-15		15	V	Full; V+ = 15 V, V- = -15 V	4
Drain-Source On-Resistance	RDS(on)		30	45	Ω	Room; IS = -10 mA, VD = ±10 V, V+ = 13.5 V, V- = -13.5 V	4
Drain-Source On-Resistance	RDS(on)			55	Ω	Full; IS = -10 mA, VD = ±10 V, V+ = 13.5 V, V- = -13.5 V	4
Δ Drain-Source On-Resistance	ΔRDS(on)			5	Ω	Full; IS = -10 mA, VD = ±5 V, 0 V; V+ = 16.5 V, V- = -16.5 V	4
Switch Off Leakage Current IS(off)	IS(off)	-0.5	-0.01	0.5	nA	Room; V+ = 16.5 V, V- = -16.5 V, VD = ±15.5 V, VS = ±15.5 V	4
Switch Off Leakage Current IS(off)	IS(off)	-5		5	nA	Hot (Full); V+ = 16.5 V, V- = -16.5 V, VD = ±15.5 V, VS = ±15.5 V	4
Switch Off Leakage Current ID(off)	ID(off)	-0.5	-0.01	0.5	nA	Room; V+ = 16.5 V, V- = -16.5 V, VD = ±15.5 V, VS = ±15.5 V	4
Switch Off Leakage Current ID(off)	ID(off)	-5		5	nA	Hot (Full); V+ = 16.5 V, V- = -16.5 V, VD = ±15.5 V, VS = ±15.5 V	4
Channel On Leakage Current	ID(on)	-1	-0.04	1	nA	Room; V+ = 16.5 V, V- = -16.5 V, VS = VD = ±15.5 V	4
Channel On Leakage Current	ID(on)	-10		10	nA	Hot (Full); V+ = 16.5 V, V- = -16.5 V, VS = VD = ±15.5 V	4
Input Current VIN Low	IIL	-1	0.005	1	µA	Full; VIN under test = 0.8 V, all other = 2.4 V	4
Input Current VIN High	IIH	-1	0.005	1	µA	Full; VIN under test = 2.4 V, all other = 0.8 V	4
Turn-On Time	tON		75	150	ns	Room; RL = 300 Ω, CL = 35 pF, see Figure 2	4
Turn-Off Time	tOFF		30	100	ns	Room	4
Positive Supply Current	I+		0.01	1	µA	Room; V+ = 16.5 V, V- = -16.5 V, VIN = 0 or 5 V	4
Positive Supply Current	I+			5	µA	Full; V+ = 16.5 V, V- = -16.5 V, VIN = 0 or 5 V	4
Negative Supply Current	I-	-1	-0.01		µA	Room	4
Negative Supply Current	I-	-5			µA	Full	4
Logic Supply Current	IL		0.01	1	µA	Room	4
Logic Supply Current	IL			5	µA	Full	4
Ground Current	IGND	-1	-0.01		µA	Room	4
Ground Current	IGND	-5			µA	Full	4
Logic input level, logic 0				0.8	V	Logic "0" as printed in functional block diagram	1
Logic input level, logic 1		2.4			V	Logic "1" as printed in functional block diagram	1
V+ to V-				44	V		3
GND to V-				25	V		3
Current (any terminal)				30	mA	Continuous	3
Current, S or D				100	mA	Pulsed 1 ms, 10 % duty	3
Storage Temperature		-65		125	°C	DY suffix	3
Power Dissipation (Package), 16-Pin SOIC				600	mW	Note d: derate 7.6 mW/°C above 75 °C	3
Operating Temperature Range		-40		85	°C	D suffix (ordering temp. range)	3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	Pc		Power Dissipation (Package)b 16-Pin Plastic DIPc 450	3

CAD (KiCad official)

Symbol: DG401DY-T1-E3
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: dg401dy-t1-e3-etched.step / dg401dy-t1-e3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dg401dy-t1-e3.step / dg401dy-t1-e3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Vishay Intertech datasheet (15 pp, sha256 ae51c49880427255, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DG401DY-T1-E3

Verified DG401DY-T1-E3

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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