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DDTC115GCA-7-F

Diodes Incorporated · Digital Transistors · SOT-23

DDTC115GCA-7-F from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B input Base input, with built-in R2 (100kΩ nominal, ±30%) bleeder resistor between base and emitter; VEBO max 5V.
2 E passive Emitter of the NPN pre-biased transistor, normally tied to ground; emitter-base voltage limited to 5V.
3 C passive Collector output; VCEO 50V max, IC max 100mA, VCE(sat) max 0.3V at IC=10mA, IB=0.5mA.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-23
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Collector-Base Breakdown Voltage BVCBO 50 V IC = 50μA 2
Collector-Emitter Breakdown Voltage BVCEO 50 V IC = 1mA 2
Emitter-Base Breakdown Voltage BVEBO 5 V IE = 72μA, DDTC115GCA 2
Collector Cutoff Current ICBO 0.5 μA VCB = 50V 2
Emitter Cutoff Current IEBO 30 58 μA VEB = 4V 2
Collector-Emitter Saturation Voltage VCE(sat) 0.3 V IC = 10mA, IB = 0.5mA 2
DC Current Transfer Ratio hFE 82 IC = 5mA, VCE = 5V 2
Bleeder Resistor (R2) Tolerance ΔR2 -30 30 % 2
Collector-Base Voltage VCBO 50 V 1
Collector-Emitter Voltage VCEO 50 V 1
Emitter-Base Voltage VEBO 5 V 1
Collector Current (Max) IC 100 mA 1
Power Dissipation PD 200 mW 1
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 1
Thermal Resistance, Junction to Ambient Air RθJA 625 °C/W Mounted on FR4 PC Board with recommended pad layout (Note 1) 1
Bleeder Resistor (R2) nominal value R2 100 KΩ 1

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin • Terminals: Solderable per MIL-STD-202, Method 208 • Lead Free Plating (Matte Tin Finish annealed over 1

CAD (KiCad official)

  • Symbol: DDTC115GCA-7-F
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: ddtc115gca-7-f-etched.step / ddtc115gca-7-f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ddtc115gca-7-f.step / ddtc115gca-7-f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (5 pp, sha256 f5b33c681562cf14, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF