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DDTC115ECA-7-F

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Diodes Incorporated Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

markdown

DDTC115ECA-7-F

Diodes Incorporated · Digital Transistors · SOT-23

DDTC115ECA-7-F from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN input Input terminal of the built-in bias network, rated at VIN -10 V to +40 V (referenced to pin 2) for the DDTC115ECA.
2 GND power_in Common ground reference; the absolute maximum VIN (pin 1 to pin 2) and VCC (pin 3 to pin 2) ratings are both referenced to this pin.
3 OUT output Output terminal of the NPN pre-biased transistor; supply voltage VCC is rated 50 V max (pin 3 to pin 2) and output current IO is rated 20 mA for the DDTC115ECA.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-23
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Resistor Tolerance R1 R1 -30 30 % 2
Resistance Ratio Tolerance R2/R1 R2/R1 0.8 1 1.2 % 2
DC Current Gain Gl 82 VO = 5V, IO = 5mA (DDTC115ECA) 2
Input Current Il 0.15 mA VI = 5V (DDTC115ECA) 2
Output Current IO(off) 0.5 μA VCC = 50V, VI = 0V 2
Output Voltage VO(on) 0.1 0.3 V IO/Il = 5mA/0.25mA, DDTC115ECA 2
Input Voltage Vl(off) 0.5 1.1 V VCC = 5V, IO = 100μA 2
Input Voltage Vl(on) 1.9 3 V VO = 0.3V, IO = 1mA, DDTC115ECA 2
Supply Voltage VCC 50 V Pin (3) to (2) 2
Input Voltage VIN -10 40 V Pin (1) to (2), DDTC115ECA 2
Output Current IO 20 mA DDTC115ECA 2
Output Current IC (Max) IC 100 mA 2
Power Dissipation PD 200 mW Note 7: mounted on FR4 PC board with minimum recommended pad layout 2
Thermal Resistance, Junction to Ambient Air RθJA 625 °C/W Note 7: mounted on FR4 PC board with minimum recommended pad layout 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2
Input Resistor R1 (NOM) R1 100 kΩ R1, R2 (NOM) for DDTC115ECA 1

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin  Terminals: Finish, Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 1

CAD (KiCad official)

  • Symbol: DDTC115ECA-7-F
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: ddtc115eca-7-f-etched.step / ddtc115eca-7-f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ddtc115eca-7-f.step / ddtc115eca-7-f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (5 pp, sha256 b71e1c1af45adb44, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF