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DDTC114EE-7-F

Public Made by Adom

by adom

Diodes Incorporated Digital Transistors, SOT-523. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DDTC114EE-7-F

Diodes Incorporated · Digital Transistors · SOT-523

DDTC114EE-7-F from Diodes Incorporated, in a SOT-523. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN input Input to the built-in bias network (R1 = R2 = 10kΩ nominal for DDTC114EE); the input voltage from pin 1 to pin 2 must stay between -10 V and +40 V.
2 GND power_in Ground reference (emitter) to which the input voltage (pin 1) and supply voltage (pin 3) are specified; the datasheet labels this pin GND (0).
3 OUT output Output (collector) of the pre-biased NPN transistor; supply voltage from pin 3 to pin 2 is rated up to 50 V, and output current for DDTC114EE is rated up to 50 mA.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-523
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input resistor tolerance (ΔR1) ΔR1 -30 30 % 3
Resistance ratio tolerance (ΔR2/R1) ΔR2/R1 0.8 1 1.2 % 3
Input voltage, OFF Vl(off) 0.5 V VCC = 5V, IO = 100µA 3
Input voltage, ON Vl(on) 3 V VO = 0.3V, IO = 10mA, DDTC114EE 3
Output voltage, ON VO(on) 0.1 0.3 V IO/Il = 10mA/0.5mA, DDTC114EE 3
Input current Il 0.88 mA VI = 5V 3
Output current, OFF IO(off) 0.5 µA VCC = 50V, VI = 0V 3
DC current gain Gl 30 VO = 5V, IO = 5mA 3
Supply voltage VCC 50 V 2
Input voltage (pin 1 to pin 2), DDTC114EE VI -10 40 V Pin (1) to (2), DDTC114EE 2
Output current, DDTC114EE IO 50 mA DDTC114EE 2
Output current IC (max) IC 100 mA 2
Power dissipation PD 150 mW Notes 5 & 6: FR-4 PCB, minimum recommended pad layout; 150mW per element must not be exceeded 2
Thermal resistance, junction to ambient RθJA 833 °C/W Note 5: mounted on FR-4 PCB, minimum recommended pad layout 2
Operating and storage temperature range TJ, TSTG -55 150 °C 2
Input resistor R1 = R2 (nominal) R1, R2 10 kΩ 1

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin • Terminals: Finish, Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 1

CAD (KiCad official)

  • Symbol: DDTC114EE-7-F
  • Footprint: Package_TO_SOT_SMD:SOT-523
  • 3D model: SOT-523, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.8 mm nominal SOT-523 height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: ddtc114ee-7-f-etched.step / ddtc114ee-7-f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ddtc114ee-7-f.step / ddtc114ee-7-f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (10 pp, sha256 56302da36e458e57, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF