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DDTA123JCA-7-F

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Diodes Incorporated Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistorsddta123jca-7-ffactory-2.0.0extractor-text

Verified DDTA123JCA-7-F

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 3 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DDTA123JCA-7-F · SOT-23 · 3 pins
  • ✓copper: 3 copper pads, none touching another net
  • ✓datasheet: all 3 pin names found in the 4-page datasheet
  • ✓distributor: lcsc C460027, digikey DDTA123JCA-FDITR-ND, mouser 621-DDTA123JCA-7-F
  • ✓family: SOT-23
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-68vrmey9/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.1)
  • ✓pads: 3 pins = 3 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 3 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 17 kB, viewers/symbol.html 7 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ddta123jca-7-f.kicad_sym✓ ddta123jca-7-f.kicad_mod✓ ddta123jca-7-f.step
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3D Model

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Symbol & Footprint

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PCB Footprint

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Datasheet

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Contents

README

markdown

DDTA123JCA-7-F

Diodes Incorporated · Digital Transistors · SOT-23

DDTA123JCA-7-F from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.

Pinout

Pin Name Type Function
1 IN input Input pin; the DDTA123JCA input voltage is rated +5 to -12 V (pin 1 to pin 2), and the input current is -3.6 mA max at VI = -5 V.
2 GND power_in Ground reference pin (marked GND(+) on the pin configuration diagram); all input and supply voltage limits are referenced to this pin.
3 OUT output Output pin (collector, with the internal bias resistors built in); the supply voltage VCC from pin 3 to pin 2 is rated -50 V max and the output current IO is -100 mA max.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-23
Category Transistors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC -50 V 1
Input Voltage VIN -12 5 V (1) to (2) 1
Output Current IO -100 mA 1
Output Current All IC (Max) -100 mA 1
Power Dissipation Pd 200 mW 2
Thermal Resistance, Junction to Ambient Air RθJA 625 °C/W Mounted on FR4 PC Board with recommended pad layout (Note 3) 2
Operating and Storage Temperature Range Tj, TSTG -55 150 °C 2
Input Voltage (off) Vl(off) -0.5 V VCC = 5V, IO = 100μA 2
Input Voltage (on) Vl(on) -1.1 V VO = -0.3V, IO = -5mA 2
Output Voltage VO(on) -0.1 -0.3 V IO/Il = -5mA/-0.25mA 2
Input Current Il -3.6 mA VI = -5V 2
Output Current (off) IO(off) -0.5 μA VCC = -50V, VI = 0V 2
DC Current Gain Gl -80 VO = -5V, IO = -10mA 2
Input Resistor Tolerance ΔR1 -30 30 % 2
Resistance Ratio Tolerance ΔR2/R1 -20 20 % 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin • Terminals: Solderable per MIL-STD-202, Method 208 • Lead Free Plating (Matte Tin Finish annealed over Alloy 1

CAD (land: KiCad; 3D: generated from the datasheet)

  • Symbol: DDTA123JCA-7-F
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23, generated on the KiCad land (body 1.3 x 2.9 mm, terminals on the pads, 1.0015 mm tall, datasheet A, midpoint of min and max). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
  • 3D model files: ddta123jca-7-f-etched.step / ddta123jca-7-f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ddta123jca-7-f.step / ddta123jca-7-f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (4 pp, sha256 77b10576bfb16755, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).

Datasheet PDF