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DDTA114TCA-7-F

Diodes Incorporated · Digital Transistors · SOT-23

DDTA114TCA-7-F from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.

Pinout

Pin Name Type Function
1 B input Base input of the PNP pre-biased transistor, with a built-in series resistor R1 of 10kΩ nominal (±30% tolerance) and a VEBO limit of -5V.
2 E passive Emitter of the PNP pre-biased transistor, with VEBO of -5V and collector current limited to -100mA.
3 C passive Collector of the PNP pre-biased transistor, with VCEO of -50V, VCBO of -50V and IC max of -100mA.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-23
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Collector-Base Breakdown Voltage BVCBO -50 V IC = -50μA 2
Collector-Emitter Breakdown Voltage BVCEO -50 V IC = -1mA 2
Emitter-Base Breakdown Voltage BVEBO -5 V IE = -50μA 2
Collector Cutoff Current ICBO -0.5 μA VCB = -50V 2
Emitter Cutoff Current IEBO -0.5 μA VEB = -4V 2
Collector-Emitter Saturation Voltage VCE(sat) -0.3 V IC/IB = -1mA/-0.1mA DDTA114TCA 2
DC Current Transfer Ratio hFE 100 250 600 IC = -1mA, VCE = -5V 2
Input Resistor (R1) Tolerance ΔR1 -30 30 % 2
Input Resistor R1 (nominal, DDTA114TCA) R1 10 kΩ 1
Collector-Base Voltage VCBO -50 V TA = +25°C 2
Collector-Emitter Voltage VCEO -50 V TA = +25°C 2
Emitter-Base Voltage VEBO -5 V TA = +25°C 2
Collector Current (Max) IC -100 mA TA = +25°C 2
Power Dissipation PD 200 mW Note 5: FR4 PC board, minimum recommended pad layout; TA = +25°C 2
Thermal Resistance, Junction to Ambient Air RθJA 625 °C/W Note 5: FR4 PC board, minimum recommended pad layout 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin • Terminals: Finish, Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 1

CAD (land: KiCad; 3D: generated from the datasheet)

  • Symbol: DDTA114TCA-7-F
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23, generated on the KiCad land (body 1.3 x 2.9 mm, terminals on the pads, 1.025 mm tall, datasheet A, nominal). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
  • 3D model files: ddta114tca-7-f-etched.step / ddta114tca-7-f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ddta114tca-7-f.step / ddta114tca-7-f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (5 pp, sha256 96d720102c63c8b8, retrieved 2026-11-12, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).

Datasheet PDF