component

DDC115EU-7-F

Public Made by Adom

by adom

Diodes Incorporated Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorsddc115eu-7-ffactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers ddc115eu-7-f: viewers · Ray 10d ago
ddc115eu-7-f-etched.glb Publish 0.1.0 · Ray 10d ago
ddc115eu-7-f-etched.step ddc115eu-7-f: factory component page (tier=mfr) · Ray 10d ago
ddc115eu-7-f-hero.glb ddc115eu-7-f: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
ddc115eu-7-f-hero.overlay.json Publish 0.1.0 · Ray 10d ago
ddc115eu-7-f.glb Publish 0.1.0 · Ray 10d ago
ddc115eu-7-f.kicad_mod Publish 0.1.0 · Ray 10d ago
ddc115eu-7-f.kicad_sym Publish 0.1.0 · Ray 10d ago
ddc115eu-7-f.lbr Publish 0.1.0 · Ray 10d ago
ddc115eu-7-f.step Publish 0.1.0 · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago

DDC115EU-7-F

Diodes Incorporated · Digital Transistors · SOT-363

DDC115EU-7-F from Diodes Incorporated, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COM1 passive Emitter of transistor 1 (COM1), the common return for the first built-in bias network of the dual NPN pre-biased transistor.
2 IN1 input Base/input of transistor 1 through its built-in input resistor R1; input voltage for DDC115EU is rated -10 V to +40 V (absolute maximum).
3 OUT2 output Collector/output of transistor 2; for DDC115EU the output current is limited to 20 mA and the supply voltage VO to 50 V (absolute maximum).
4 COM2 passive Emitter of transistor 2 (COM2), the common return for the second built-in bias network of the dual transistor.
5 IN2 input Base/input of transistor 2 through its built-in input resistor R1; input voltage for DDC115EU is rated -10 V to +40 V (absolute maximum).
6 OUT1 output Collector/output of transistor 1; for DDC115EU the output current is limited to 20 mA and the supply voltage VO to 50 V (absolute maximum).

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-363
Category Transistors/Thyristors
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Resistor (R1) nominal R1 100 kΩ R1 (NOM) for DDC115EU 1
Resistor R2 nominal R2 100 kΩ R2 (NOM) for DDC115EU 1
Input Resistor (R1) Tolerance R1 -30 30 % 3
Resistance Ratio Tolerance R2/R1 -20 20 % 3
Supply Voltage VO 50 V 2
Input Voltage VI -10 40 V DDC115EU 2
Output Current IO 20 mA DDC115EU 2
Peak Output Current ICM 100 mA 2
Power Dissipation PD 200 mW Notes 6 & 7; 150mW per element must not be exceeded 2
Thermal Resistance, Junction to Ambient Air RθJA 625 °C/W Note 6: mounted on FR-4 PC board with minimum recommended pad layout 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2
Input Voltage VI(off) VI(off) 0.5 V VCC = 5V, IO = 100μA 3
Input Voltage VI(on) VI(on) 3 V VO = 0.3V, IO = 1mA 3
Output Voltage VO(on) VO(on) 0.1 0.3 V IO/II = 10mA / 0.5mA 3
Input Current II 0.15 mA VI = 5V 3
Output Current IO(off) IO(off) 0.5 μA VCC = 50V, VI = 0V 3
DC Current Gain GI 82 VO = 5V, IO = 5mA 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin  Terminals: Finish, Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 1

CAD (KiCad official)

  • Symbol: DDC115EU-7-F
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SOT-363 (KiCad packages3D, STEP)
  • 3D model files: ddc115eu-7-f-etched.step / ddc115eu-7-f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ddc115eu-7-f.step / ddc115eu-7-f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (8 pp, sha256 734b84dde0b96a22, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF