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DDC114EUQ-7-F
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Diodes Incorporated Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DDC114EUQ-7-F
Diodes Incorporated · Digital Transistors · SOT-363
DDC114EUQ-7-F from Diodes Incorporated, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E1 | power_in | Common emitter reference for the first pre-biased NPN; the datasheet ties the input (pin 2) and supply (pin 6) ratings to this pin, with VIN limited to -10 to +40 V for DDC114EU. |
| 2 | IN1 (input, pin 2) | input | Input of the first pre-biased transistor, rated -10 to +40 V relative to pin 1 for DDC114EU (absolute maximum ratings). |
| 3 | C2 (collector/output, pin 3) | output | Collector output of the second transistor; the supply rating of 50 V max is specified from pin 3 to pin 4. |
| 4 | E2 (GND reference, pin 4) | power_in | Common emitter reference for the second pre-biased NPN; the datasheet references the second input (pin 5) and supply (pin 3) to this pin. |
| 5 | IN2 (input, pin 5) | input | Input of the second pre-biased transistor, rated -10 to +40 V relative to pin 4 for DDC114EU (absolute maximum ratings). |
| 6 | C1 (collector/output, pin 6) | output | Collector output of the first transistor; the supply rating of 50 V max is specified from pin 6 to pin 1, with output current limited to 50 mA for DDC114EU. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage (OFF) | VI(OFF) | 0.5 | V | VCC = 5V, IO = 100μA | 3 | ||
| Input Voltage (ON) | VI(ON) | 3 | V | VO = 0.3V, IO = 10mA | 3 | ||
| Output Voltage (ON) | VO(ON) | 0.1 | 0.3 | V | IO/IL = 10mA / 0.5mA | 3 | |
| Input Current | II | 0.88 | mA | VI = 5V | 3 | ||
| Output Current (OFF) | IO(OFF) | 0.5 | μA | VCC = 50V, VI = 0V | 3 | ||
| DC Current Gain | GI | 30 | VO = 5V, IO = 5mA | 3 | |||
| Input Resistor (R1) Tolerance | ∆R1 | -30 | 30 | % | 3 | ||
| Resistance Ratio Tolerance | ∆(R2/R1) | -20 | 20 | % | 3 | ||
| Gain-Bandwidth Product (transistor, for reference only) | fT | 250 | MHz | VCE = 10V, IE = 5mA, f = 100MHz | 3 | ||
| Input Resistor R1 (NOM) | R1 | 10 | kΩ | 1 | |||
| Input Resistor R2 (NOM) | R2 | 10 | kΩ | 1 | |||
| Supply Voltage (Pin 6 to 1 and 3 to 4) | VCC | 50 | V | 2 | |||
| Input Voltage (Pin 2 to 1 and 5 to 4) | VIN | -10 | 40 | V | DDC114EU | 2 | |
| Output Current | IO | 50 | mA | DDC114EU | 2 | ||
| Output Current (maximum) | IC(MAX) | 100 | mA | 2 | |||
| Power Dissipation | PD | 200 | mW | Mounted on FR-4 PC board with minimum recommended pad layout; 150mW per element must not be exceeded | 2 | ||
| Thermal Resistance, Junction to Ambient Air | RθJA | 625 | °C/W | Mounted on FR-4 PC board with minimum recommended pad layout | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | • Terminals: Finish, Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 | 1 |
CAD (KiCad official)
- Symbol:
DDC114EUQ-7-F - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files:
ddc114euq-7-f-etched.step/ddc114euq-7-f-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ddc114euq-7-f.step/ddc114euq-7-f.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (9 pp, sha256
af0fe946c49e55f1, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DDC114EUQ-7-F
**Diodes Incorporated** · Digital Transistors · SOT-363
DDC114EUQ-7-F from Diodes Incorporated, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E1 | power_in | Common emitter reference for the first pre-biased NPN; the datasheet ties the input (pin 2) and supply (pin 6) ratings to this pin, with VIN limited to -10 to +40 V for DDC114EU. |
| 2 | IN1 (input, pin 2) | input | Input of the first pre-biased transistor, rated -10 to +40 V relative to pin 1 for DDC114EU (absolute maximum ratings). |
| 3 | C2 (collector/output, pin 3) | output | Collector output of the second transistor; the supply rating of 50 V max is specified from pin 3 to pin 4. |
| 4 | E2 (GND reference, pin 4) | power_in | Common emitter reference for the second pre-biased NPN; the datasheet references the second input (pin 5) and supply (pin 3) to this pin. |
| 5 | IN2 (input, pin 5) | input | Input of the second pre-biased transistor, rated -10 to +40 V relative to pin 4 for DDC114EU (absolute maximum ratings). |
| 6 | C1 (collector/output, pin 6) | output | Collector output of the first transistor; the supply rating of 50 V max is specified from pin 6 to pin 1, with output current limited to 50 mA for DDC114EU. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage (OFF) | VI(OFF) | | | 0.5 | V | VCC = 5V, IO = 100μA | 3 |
| Input Voltage (ON) | VI(ON) | 3 | | | V | VO = 0.3V, IO = 10mA | 3 |
| Output Voltage (ON) | VO(ON) | | 0.1 | 0.3 | V | IO/IL = 10mA / 0.5mA | 3 |
| Input Current | II | | | 0.88 | mA | VI = 5V | 3 |
| Output Current (OFF) | IO(OFF) | | | 0.5 | μA | VCC = 50V, VI = 0V | 3 |
| DC Current Gain | GI | 30 | | | | VO = 5V, IO = 5mA | 3 |
| Input Resistor (R1) Tolerance | ∆R1 | -30 | | 30 | % | | 3 |
| Resistance Ratio Tolerance | ∆(R2/R1) | -20 | | 20 | % | | 3 |
| Gain-Bandwidth Product (transistor, for reference only) | fT | | 250 | | MHz | VCE = 10V, IE = 5mA, f = 100MHz | 3 |
| Input Resistor R1 (NOM) | R1 | | 10 | | kΩ | | 1 |
| Input Resistor R2 (NOM) | R2 | | 10 | | kΩ | | 1 |
| Supply Voltage (Pin 6 to 1 and 3 to 4) | VCC | | | 50 | V | | 2 |
| Input Voltage (Pin 2 to 1 and 5 to 4) | VIN | -10 | | 40 | V | DDC114EU | 2 |
| Output Current | IO | | | 50 | mA | DDC114EU | 2 |
| Output Current (maximum) | IC(MAX) | | | 100 | mA | | 2 |
| Power Dissipation | PD | | | 200 | mW | Mounted on FR-4 PC board with minimum recommended pad layout; 150mW per element must not be exceeded | 2 |
| Thermal Resistance, Junction to Ambient Air | RθJA | | 625 | | °C/W | Mounted on FR-4 PC board with minimum recommended pad layout | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 | | 150 | °C | | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | • Terminals: Finish, Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 | 1 |
## CAD (KiCad official)
- Symbol: `DDC114EUQ-7-F`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files: `ddc114euq-7-f-etched.step` / `ddc114euq-7-f-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ddc114euq-7-f.step` / `ddc114euq-7-f.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603173971986690048) (9 pp, sha256 `af0fe946c49e55f1`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ddc114euq-7-f-datasheet.pdf)