component

DDC112YK

Public Made by Adom

by adom

Texas Instruments Analog To Digital Converters (ADC), TQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionddc112ykfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

DDC112YK

Texas Instruments · Analog To Digital Converters (ADC) · TQFP-32(7x7)

DDC112YK from Texas Instruments, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CAP1A passive External capacitor connection for Integrator 1A; pins 1 and 2 must be tied together as the side-A external integration capacitor when RANGE2-RANGE0 = 000.
2 CAP1A passive External capacitor connection for Integrator 1A; pins 1 and 2 must be tied together as the side-A external integration capacitor when RANGE2-RANGE0 = 000.
3 AVDD power_in Analog supply, +5V nominal, with AVDD and DVDD specified at 4.75 V to 5.25 V.
4 NC unconnected No connection; leave unconnected.
5 NC unconnected No connection; leave unconnected.
6 TEST input Test control input; when HIGH, a test charge of about 13 pC is applied to the A or B integrators on the next CONV transition.
7 CONV input Selects which integrator side is connected to the input; in continuous mode CONV HIGH selects side A integrating and CONV LOW selects side B integrating, and CONV must be synchronized with CLK.
8 CLK input System clock input, 10 MHz nominal (specified 10 MHz to 12 MHz for DDC112U/Y and up to 15 MHz for the YK grade).
9 DCLK input Serial data clock input that operates the serial I/O shift register, specified up to 15 MHz.
10 DXMIT input Serial data transmit enable input; when LOW it enables the internal serial shift register.
11 DIN input Serial digital input used to cascade multiple DDC112 devices.
12 DVDD power_in Digital supply, +5V nominal, with AVDD and DVDD specified at 4.75 V to 5.25 V.
13 DGND power_in Digital ground.
14 DOUT tri_state Serial data output that is high-impedance when DXMIT is HIGH.
15 DVALID output Data valid output; a LOW value indicates valid data is available in the serial I/O register.
16 RANGE0 input Range control input 0, least significant bit of the 3-bit full-scale range select.
17 RANGE1 input Range control input 1 of the 3-bit full-scale range select.
18 RANGE2 input Range control input 2, most significant bit of the 3-bit full-scale range select.
19 NC unconnected No connection; leave unconnected.
20 NC unconnected No connection; leave unconnected.
21 AGND power_in Analog ground.
22 VREF power_in External reference input, +4.096 V nominal (4.000 V to 4.200 V specified), used to reset the integrators and as the ΔΣ converter reference.
23 CAP2A passive External capacitor connection for Integrator 2A; pins 23 and 24 are tied together as the side-A external capacitor when RANGE2-RANGE0 = 000.
24 CAP2A passive External capacitor connection for Integrator 2A; pins 23 and 24 are tied together as the side-A external capacitor when RANGE2-RANGE0 = 000.
25 CAP2B passive External capacitor connection for Integrator 2B; pins 25 and 26 are tied together as the side-B external capacitor when RANGE2-RANGE0 = 000.
26 CAP2B passive External capacitor connection for Integrator 2B; pins 25 and 26 are tied together as the side-B external capacitor when RANGE2-RANGE0 = 000.
27 AGND power_in Analog ground.
28 IN2 input Analog input for Integrators 2A and 2B; the active integrator is set by the CONV input.
29 IN1 input Analog input for Integrators 1A and 1B; the active integrator is set by the CONV input.
30 AGND power_in Analog ground.
31 CAP1B passive External capacitor connection for Integrator 1B; pins 31 and 32 are tied together as the side-B external capacitor when RANGE2-RANGE0 = 000.
32 CAP1B passive External capacitor connection for Integrator 1B; pins 31 and 32 are tied together as the side-B external capacitor when RANGE2-RANGE0 = 000.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-32(7x7)
Category Data Acquisition
Pins 32

CAD (KiCad official)

  • Symbol: DDC112YK
  • Footprint: Package_QFP:TQFP-32_7x7mm_P0.8mm
  • 3D model: TQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: ddc112yk-etched.step / ddc112yk-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ddc112yk.step / ddc112yk.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 563a1029aa722041, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF