component

DALC112S1RL

Public Made by Adom

by adom

STMicroelectronics ESD And Surge Protection (TVS/ESD), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs dalc112s1rl: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers dalc112s1rl: viewers · Ray
dalc112s1rl-etched.fit.json dalc112s1rl: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dalc112s1rl-etched.glb dalc112s1rl: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dalc112s1rl-etched.step dalc112s1rl: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dalc112s1rl.glb Publish 0.1.0 · Ray
dalc112s1rl.kicad_mod Publish 0.1.0 · Ray
dalc112s1rl.kicad_sym Publish 0.1.0 · Ray
dalc112s1rl.lbr Publish 0.1.0 · Ray
dalc112s1rl.step Publish 0.1.0 · Ray
package.json dalc112s1rl: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json dalc112s1rl: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/dalc112s1rl · Ray

DALC112S1RL

STMicroelectronics · ESD And Surge Protection (TVS/ESD) · SOIC-8

DALC112S1RL from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O 5 bidirectional Signal line 5 protected by diode clamping pair to reference voltages with VRRM = 18V per diode and capacitance < 5pF.
2 I/O 6 bidirectional Signal line 6 protected by diode clamping pair to reference voltages with VRRM = 18V per diode and capacitance < 5pF.
3 I/O 1 bidirectional Signal line 1 protected by diode clamping pair to reference voltages with VRRM = 18V per diode and capacitance < 5pF.
4 I/O 2 bidirectional Signal line 2 protected by diode clamping pair to reference voltages with VRRM = 18V per diode and capacitance < 5pF.
5 I/O 3 bidirectional Signal line 3 protected by diode clamping pair to reference voltages with VRRM = 18V per diode and capacitance < 5pF.
6 I/O 4 bidirectional Signal line 4 protected by diode clamping pair to reference voltages with VRRM = 18V per diode and capacitance < 5pF.
7 REF 1 power_in Positive supply voltage reference connection for diode clamping, +VCC connected between REF1 and REF2.
8 REF 2 power_in Ground/negative supply reference connection for diode clamping, +VCC connected between REF1 and REF2.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-8
Category Circuit Protection
Pins 8

CAD (KiCad official)

  • Symbol: DALC112S1RL
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: dalc112s1rl-etched.step / dalc112s1rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dalc112s1rl.step / dalc112s1rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (3 pp, sha256 a7e89c8091e633cb, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF