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DAC9881SRGER

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Texas Instruments Digital To Analog Converters (DACs), VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified DAC9881SRGER

by Ray · last 2 Nov 2026 · 1 record · files match
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2 Nov 2026RayPublished by the parts factory: tier mfr, 25 pinsfiles match
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC9881SRGER · VQFN-24-EP(4x4) · 25 pins
  • ✓copper: 25 copper pads, none touching another net
  • ✓datasheet: all 25 pin names found in the 46-page datasheet
  • ✓distributor: lcsc C1555360, digikey DAC9881SRGER-ND, mouser 595-DAC9881SRGER
  • ✓family: QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-9sg0n__9/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 25 pins = 25 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 25 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dac9881srger.kicad_sym✓ dac9881srger.kicad_mod✓ dac9881srger.step
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Contents

README

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DAC9881SRGER

Texas Instruments · Digital To Analog Converters (DACs) · VQFN-24-EP(4x4)

DAC9881SRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input SPI bus serial clock input.
2 SDI input SPI bus serial data input.
3 LDAC input Load DAC latch control input (active low); when low the DAC latch is transparent and the DAC output updates, and it is recommended to pull this pin up to IOVDD through a resistor.
4 AGND power_in Analog ground.
5 AVDD power_in Analog power supply, which must be connected to pin 21; the supply range is 2.7 V to 5.5 V.
6 VREFL-S input Reference low input sense.
7 VREFH-S input Reference high input sense.
8 VOUT output Output of the output buffer.
9 RFB input Feedback resistor connected to the inverting input of the output buffer.
10 VREFL-F input Reference low input force.
11 VREFH-F input Reference high input force.
12 NC unconnected Do not connect.
13 NC unconnected Do not connect.
14 RSTSEL input Selects the VOUT value after power-on or hardware reset: IOVDD gives register data 20000h and DGND gives 00000h.
15 GAIN input Buffer gain setting: gain is 1 when connected to DGND and 2 when connected to IOVDD.
16 USB/BTC input Input data format selection: straight binary when connected to IOVDD and two's complement when connected to DGND.
17 RST input Reset input (active low); a logic low on this pin causes the device to reset.
18 PDN input Power-down input (active high); a logic high forces power-down, during which VOUT connects to AGND through a 10-kΩ resistor.
19 CS input SPI bus chip select input (active low); data is clocked into the shift register only when CS is low, and SDO is high-impedance when CS is high.
20 SDOSEL input SPI serial data output selection: IOVDD selects stand-alone mode (input register shifted out) and DGND selects daisy-chain mode (shift register shifted out).
21 AVDD power_in Analog power supply, which must be connected to pin 5; the supply range is 2.7 V to 5.5 V.
22 DGND power_in Digital ground.
23 SDO output SPI bus serial data output; refer to the timing diagrams for detail.
24 IOVDD power_in Interface power; connect to 1.8 V for 1.8-V logic, 3 V for 3-V logic, or 5 V for 5-V logic, with a range of 1.7 V to AVDD.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Data Converters
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog power supply AVDD 2.7 5.5 V 5
Interface power supply IOVDD 1.7 V 5
Reference high input voltage VREFH 1.25 5 V AVDD = 5.5 V 5
Reference high input voltage VREFH 1.25 2.5 V AVDD = 3 V 5
Reference low input voltage VREFL -0.2 0 0.2 V 5
Specified temperature TA -40 105 °C 5
AVDD to AGND AVDD -0.3 6 V 5
IOVDD to DGND IOVDD -0.3 6 V 5
Digital input voltage to DGND -0.3 V 5
VOUT to AGND VOUT -0.3 V 5
Maximum junction temperature TJ 150 °C 5
Storage temperature Tstg -65 150 °C 5
Integral linearity error -3 2 3 LSB Measured by line passing through codes 2048 and 260096 6
Differential linearity error -1 0.75 2 LSB Measured by line passing through codes 2048 and 260096 6
Zero-scale error -16 16 LSB TA = 25°C, code = 2048 6
Zero-scale error -32 32 LSB TMIN to TMAX, code = 2048 6
Zero-scale drift -0.8 0.25 0.8 ppm/°C of FSR Code = 2048 6
Gain error -32 16 32 LSB TA = 25°C, measured by line passing through codes 2048 and 260096 6
Gain temperature drift -0.4 0.25 0.4 ppm/°C Measured by line passing through codes 2048 and 260096 6
Short-circuit current -50 31 mA 6
VREFH input voltage range VREFH 1.25 5 V AVDD = 5.5 V 6
VREFL input voltage range VREFL -0.2 0 0.2 V 6
High-level input voltage, VIH VIH 3.8 V IOVDD = 4.5 V to 5.5 V 7
Low-level input voltage, VIL VIL -0.3 0.8 V IOVDD = 4.5 V to 5.5 V 7
Digital input current IIN -10 1 10 µA 7
Low-level output voltage, VOL VOL 0.2 V IOVDD = 2.7V to 5.5 V, IOL = 1 mA 7
Analog power supply AVDD 4.75 5 5.5 V 7
AVDD supply current AIDD 0.85 1.5 mA VIH = IOVDD, VIL = DGND 7
IOVDD supply current IOIDD 1 10 µA VIH = IOVDD, VIL = DGND 7
AVDD power-down current AIDD 25 50 µA PDN pin = IOVDD 7
Power dissipation 4.3 7.5 mW AVDD = 5 V 7
Integral linearity error -3.5 2.5 3.5 LSB Measured by line passing through codes 2048 and 262143 8
Differential linearity error -2 1 2 LSB Measured by line passing through codes 2048 and 262143 8
Zero-scale error -32 32 LSB TA = 25°C, code = 2048 8
Zero-scale error -64 64 LSB TMIN to TMAX, code = 2048 8
Zero-scale drift -1.6 0.5 1.6 ppm/°C of FSR Code = 2048 8
Gain error -64 32 64 LSB TA = 25°C, measured by line passing through codes 2048 and 262143 8
Gain temperature drift -0.8 0.5 0.8 ppm/°C Measured by line passing through codes 2048 and 262143 8
High-level input voltage, VIH VIH 2.1 V IOVDD = 2.7 V to 3.3 V 9
Low-level input voltage, VIL VIL -0.3 0.6 V IOVDD = 2.7 V to 3.3 V 9
Digital input current IIN -10 1 10 µA 9
Analog power supply AVDD 2.7 3 3.3 V 9
AVDD supply current AIDD 0.75 1.2 mA VIH = IOVDD, VIL = DGND 9
IOVDD supply current IOIDD 1 10 µA VIH = IOVDD, VIL = DGND 9
AVDD power-down current AIDD 25 50 µA PDN pin = IOVDD 9
Power dissipation 2.3 3.6 mW AVDD = 3 V 9
Maximum clock frequency fSCLK 50 MHz 3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 10
Maximum clock frequency fSCLK 40 MHz 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 10
SCLK cycle time t6 20 ns 3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD 10
SCLK cycle time t6 25 ns 2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD 10
Junction-to-ambient thermal resistance RθJA 33.5 °C/W 5
Junction-to-case (top) thermal resistance RθJC(top) 37.1 °C/W 5
Junction-to-board thermal resistance RθJB 11.3 °C/W 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 2 °C/W 5

CAD (KiCad official)

  • Symbol: DAC9881SRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: dac9881srger-etched.step / dac9881srger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac9881srger.step / dac9881srger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 c35ae6ca8da8a412, retrieved 2026-11-02, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF