component
DAC904U
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Texas Instruments Digital To Analog Converters (DAC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+64@@ -0,0 +1,64 @@+# DAC904U++**Texas Instruments** · Digital To Analog Converters (DAC) · SOIC-28-300mil++DAC904U from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Bit 1 (D13) | input | Data bit 1, the MSB (D13) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 2 | Bit 2 (D12) | input | Data bit 2 (D12) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 3 | Bit 3 (D11) | input | Data bit 3 (D11) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 4 | Bit 4 (D10) | input | Data bit 4 (D10) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 5 | Bit 5 (D9) | input | Data bit 5 (D9) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 6 | Bit 6 (D8) | input | Data bit 6 (D8) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 7 | Bit 7 (D7) | input | Data bit 7 (D7) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 8 | Bit 8 (D6) | input | Data bit 8 (D6) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 9 | Bit 9 (D5) | input | Data bit 9 (D5) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 10 | Bit 10 (D4) | input | Data bit 10 (D4) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 11 | Bit 11 (D3) | input | Data bit 11 (D3) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 12 | Bit 12 (D2) | input | Data bit 12 (D2) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 13 | Bit 13 (D1) | input | Data bit 13 (D1) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 14 | Bit 14 (D0) | input | Data bit 14 (D0), the LSB of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic. |+| 15 | PD | input | Power-down control input, active HIGH; it has an internal pull-down (about 45µA typical) and may be left unconnected if not used. |+| 16 | INT/EXT | input | Reference select: internal reference when low (=0) and external reference when high (=1). |+| 17 | REFIN | bidirectional | Reference input/output; reference input compliance range is 0.1V to 1.25V, and the Applications section gives further details. |+| 18 | FSA | input | Full-scale output adjust; one external resistor sets the full-scale output current over a 2mA to 20mA span while keeping the specified dynamic performance. |+| 19 | BW | passive | Bandwidth/noise reduction pin; bypass with 0.1µF to +VA for optimum performance (optional). |+| 20 | AGND | power_in | Analog ground; AGND to DGND is limited to -0.3V to +0.3V per the absolute maximum ratings. |+| 21 | IOUT | output | Complementary DAC current output; IOUT to AGND is limited to -1V to VA + 0.3V. |+| 22 | IOUT | output | DAC current output; output compliance range is -1.0V to +1.25V, with nominal full scale of 20mA. |+| 23 | BYP | passive | Bypass node; use 0.1µF to AGND. |+| 24 | +VA | power_in | Analog supply voltage, 2.7V to 5.5V (absolute maximum +VA to AGND is -0.3V to +6V). |+| 25 | NC | unconnected | No internal connection. |+| 26 | DGND | power_in | Digital ground. |+| 27 | +VD | power_in | Digital supply voltage, 2.7V to 5.5V (absolute maximum +VD to DGND is -0.3V to +6V). |+| 28 | CLK | input | Clock input; data is latched on the rising edge, with minimum clock pulse high and low times of 3ns. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-28-300mil |+| Category | Data Acquisition |+| Pins | 28 |++## CAD (KiCad official)++- Symbol: `DAC904U`+- Footprint: `Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm`+- 3D model: SOIC-28-300mil (KiCad packages3D, STEP)+- 3D model files: `dac904u-etched.step` / `dac904u-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac904u.step` / `dac904u.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac904) (24 pp, sha256 `07f1171133bbfb0f`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac904u-datasheet.pdf)
page.jsonadded+320@@ -0,0 +1,320 @@+{+ "slug": "dac904u",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Digital To Analog Converters (DAC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "dac904u",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dac904u.kicad_sym",+ "dac904u.kicad_mod",+ "dac904u.glb",+ "dac904u.step",+ "dac904u.lbr",+ "docs/hero.png",+ "docs/dac904u-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dac904u-hero.glb",+ "dac904u-hero.overlay.json"+ ],+ "component": {+ "mpn": "DAC904U",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-28-300mil",+ "pin_count": 28,+ "category": "Data Acquisition",+ "subcategory": "Digital To Analog Converters (DAC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dac904",+ "parts": {+ "symbol": "dac904u.kicad_sym",+ "footprint": "dac904u.kicad_mod",+ "model_3d": "dac904u-hero.glb",+ "model_3d_plain": "dac904u.glb",+ "model_3d_step": "dac904u-etched.step",+ "model_3d_step_plain": "dac904u.step",+ "lbr": "dac904u.lbr"+ },+ "distributor_links": {+ "lcsc": "C1554816",+ "digikey": "2156-DAC904U-ND",+ "mouser": "595-DAC904U"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T20:03:23Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-DAC904U-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DAC904U",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "Bit 1 (D13)",+ "type": "input",+ "description": "Data bit 1, the MSB (D13) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "2",+ "name": "Bit 2 (D12)",+ "type": "input",+ "description": "Data bit 2 (D12) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "3",+ "name": "Bit 3 (D11)",+ "type": "input",+ "description": "Data bit 3 (D11) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "4",+ "name": "Bit 4 (D10)",+ "type": "input",+ "description": "Data bit 4 (D10) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "5",+ "name": "Bit 5 (D9)",+ "type": "input",+ "description": "Data bit 5 (D9) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "6",+ "name": "Bit 6 (D8)",+ "type": "input",+ "description": "Data bit 6 (D8) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "7",+ "name": "Bit 7 (D7)",+ "type": "input",+ "description": "Data bit 7 (D7) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "8",+ "name": "Bit 8 (D6)",+ "type": "input",+ "description": "Data bit 8 (D6) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "9",+ "name": "Bit 9 (D5)",+ "type": "input",+ "description": "Data bit 9 (D5) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "10",+ "name": "Bit 10 (D4)",+ "type": "input",+ "description": "Data bit 10 (D4) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "11",+ "name": "Bit 11 (D3)",+ "type": "input",+ "description": "Data bit 11 (D3) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "12",+ "name": "Bit 12 (D2)",+ "type": "input",+ "description": "Data bit 12 (D2) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "13",+ "name": "Bit 13 (D1)",+ "type": "input",+ "description": "Data bit 13 (D1) of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "14",+ "name": "Bit 14 (D0)",+ "type": "input",+ "description": "Data bit 14 (D0), the LSB of the 14-bit straight-binary input word, latched on the rising clock edge and interfaceable with +3V or +5V CMOS logic."+ },+ {+ "number": "15",+ "name": "PD",+ "type": "input",+ "description": "Power-down control input, active HIGH; it has an internal pull-down (about 45µA typical) and may be left unconnected if not used."+ },+ {+ "number": "16",+ "name": "INT/EXT",+ "type": "input",+ "description": "Reference select: internal reference when low (=0) and external reference when high (=1)."+ },+ {+ "number": "17",+ "name": "REFIN",+ "type": "bidirectional",+ "description": "Reference input/output; reference input compliance range is 0.1V to 1.25V, and the Applications section gives further details."+ },+ {+ "number": "18",+ "name": "FSA",+ "type": "input",+ "description": "Full-scale output adjust; one external resistor sets the full-scale output current over a 2mA to 20mA span while keeping the specified dynamic performance."+ },+ {+ "number": "19",+ "name": "BW",+ "type": "passive",+ "description": "Bandwidth/noise reduction pin; bypass with 0.1µF to +VA for optimum performance (optional)."+ },+ {+ "number": "20",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; AGND to DGND is limited to -0.3V to +0.3V per the absolute maximum ratings."+ },+ {+ "number": "21",+ "name": "IOUT",+ "type": "output",+ "description": "Complementary DAC current output; IOUT to AGND is limited to -1V to VA + 0.3V."+ },+ {+ "number": "22",+ "name": "IOUT",+ "type": "output",+ "description": "DAC current output; output compliance range is -1.0V to +1.25V, with nominal full scale of 20mA."+ },+ {+ "number": "23",+ "name": "BYP",+ "type": "passive",+ "description": "Bypass node; use 0.1µF to AGND."+ },+ {+ "number": "24",+ "name": "+VA",+ "type": "power_in",+ "description": "Analog supply voltage, 2.7V to 5.5V (absolute maximum +VA to AGND is -0.3V to +6V)."+ },+ {+ "number": "25",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "26",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "27",+ "name": "+VD",+ "type": "power_in",+ "description": "Digital supply voltage, 2.7V to 5.5V (absolute maximum +VD to DGND is -0.3V to +6V)."+ },+ {+ "number": "28",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; data is latched on the rising edge, with minimum clock pulse high and low times of 3ns."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet gives the SO-28 pinout (DW package) as a single table shared with TSSOP-28; the DW pac; Pin types are KiCad ERC classes inferred from the functional descriptions. REFIN is typed bidirectio; Pin names are given as printed (Bit 1 to Bit 14) with the datasheet's D13 to D0 designations in pare"+ ],+ "pages_sent": 8,+ "cost_usd": 0.0712,+ "at": "2026-10-08T20:02:57"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dac904",+ "pages": 24,+ "sha256": "07f1171133bbfb0f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 28,+ "described": 28,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dac904u.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 17.9,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b889a13dbe9ec59e79fa9f1b5118b00bfa54f9582392335ff3365b64afc264b1",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac904u-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 17.9,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "466baf4a36f21674c9c1352d5c5930dba3e1a0dfce92551dc8b2e19bcc8fd200",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}