main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers dac900u: viewers · Ray
dac900u-etched.glb Publish 0.1.0 · Ray
dac900u-etched.step dac900u: factory component page (tier=mfr) · Ray
dac900u-hero.glb dac900u: hero GLB from the etched model (keeps the MPN mark) · Ray
dac900u-hero.overlay.json Publish 0.1.0 · Ray
dac900u.glb Publish 0.1.0 · Ray
dac900u.kicad_mod Publish 0.1.0 · Ray
dac900u.kicad_sym Publish 0.1.0 · Ray
dac900u.lbr Publish 0.1.0 · Ray
dac900u.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 28 pins · Ray

DAC900U

Texas Instruments · Digital To Analog Converters (DAC) · SOIC-28-300mil

DAC900U from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Bit 1 input Data bit 1 (D9), MSB of the 10-bit parallel data input.
2 Bit 2 input Data bit 2 (D8) of the 10-bit parallel data input.
3 Bit 3 input Data bit 3 (D7) of the 10-bit parallel data input.
4 Bit 4 input Data bit 4 (D6) of the 10-bit parallel data input.
5 Bit 5 input Data bit 5 (D5) of the 10-bit parallel data input.
6 Bit 6 input Data bit 6 (D4) of the 10-bit parallel data input.
7 Bit 7 input Data bit 7 (D3) of the 10-bit parallel data input.
8 Bit 8 input Data bit 8 (D2) of the 10-bit parallel data input.
9 Bit 9 input Data bit 9 (D1) of the 10-bit parallel data input.
10 Bit 10 input Data bit 10 (D0), LSB of the 10-bit parallel data input.
11 NC unconnected No connection.
12 NC unconnected No connection.
13 NC unconnected No connection.
14 NC unconnected No connection.
15 PD input Power-down control input, active HIGH; it contains an internal pull-down circuit and may be left unconnected if not used.
16 INT/EXT input Reference select pin: internal reference when low (=0) and external reference when high (=1).
17 REFIN bidirectional Reference input/output; see the Applications section for further details.
18 FSA passive Full-scale output adjust pin, used with one external resistor to set the full-scale output current over 2mA to 20mA.
19 BW passive Bandwidth/noise reduction pin; bypass with 0.1µF to +VA for optimum performance.
20 AGND power_in Analog ground.
21 IOUT output Complementary DAC current output.
22 IOUT output DAC current output; output compliance range is -1.0V to +1.25V.
23 BYP passive Bypass node; use 0.1µF to AGND.
24 +VA power_in Analog supply voltage, 2.7V to 5.5V.
25 NC unconnected No connection.
26 DGND power_in Digital ground.
27 +VD power_in Digital supply voltage, 2.7V to 5.5V.
28 CLK input Clock input; data is latched on the rising edge of the clock.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-28-300mil
Category Data Acquisition
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Update Rate fCLOCK 125 165 MSPS 2.7V to 3.3V 2
Output Update Rate fCLOCK 165 200 MSPS 4.5V to 5.5V 2
Full Specified Temperature Range, Operating Ambient TA -40 85 °C Full Specified Temperature Range 2
Differential Nonlinearity DNL -0.5 0.3 0.5 LSB fCLOCK = 25MSPS, fOUT = 1.0MHz 2
Integral Nonlinearity INL -1 0.5 1 LSB 2
Spurious-Free Dynamic Range SFDR 70 76 dBc fOUT = 1.0MHz, fCLOCK = 25MSPS 2
Full-Scale Output Range FSR 2 20 mA All Bits High, IOUT 3
Output Compliance Range -1 1.25 V 3
Gain Error -10 1 10 %FSR With Internal Reference 3
Gain Error -10 2 10 %FSR With External Reference 3
Gain Drift -120 120 ppmFSR/°C With Internal Reference 3
Offset Error -0.025 0.025 %FSR With Internal Reference 3
Offset Drift -0.1 0.1 ppmFSR/°C With Internal Reference 3
Power-Supply Rejection, +VA -0.2 0.2 %FSR/V 3
Power-Supply Rejection, +VD -0.025 0.025 %FSR/V 3
Reference Tolerance -10 10 % 3
Reference Voltage Drift -50 50 ppmFSR/°C 3
Reference Input Compliance Range 0.1 1.25 V 3
Logic High Voltage, VIH VIH 3.5 5 V +VD = +5V 3
Logic Low Voltage, VIL VIL 0 1.2 V +VD = +5V 3
Logic High Voltage, VIH VIH 2 3 V +VD = +3V 3
Logic Low Voltage, VIL VIL 0 0.8 V +VD = +3V 3
Logic High Current IIH -20 20 µA +VD = +5V 3
Logic Low Current IIL -20 20 µA +VD = +5V 3
Supply Voltage, +VA +VA 2.7 5 5.5 V 3
Supply Voltage, +VD +VD 2.7 5 5.5 V 3
Supply Current IVA 24 30 mA 3
Supply Current, Power-Down Mode IVA 1.1 2 mA Power-Down Mode 3
Supply Current IVD 8 15 mA 3
Power Dissipation 170 230 mW +5V, IOUT = 20mA 3
Thermal Resistance, θJA θJA 75 °C/W SO-28 3
+VA to AGND +VA -0.3 6 V 2
+VD to DGND +VD -0.3 6 V 2
AGND to DGND -0.3 0.3 V 2
+VA to +VD -6 6 V 2
CLK, PD to DGND -0.3 V 2
D0-D9 to DGND -0.3 V 2
IOUT, IOUT to AGND -1 V 2
BW, BYP to AGND -0.3 V 2
REFIN, FSA to AGND -0.3 V 2
INT/EXT to AGND -0.3 V 2
Junction Temperature 150 °C 2
Case Temperature 100 °C 2
Storage Temperature 125 °C 2

CAD (KiCad official)

  • Symbol: DAC900U
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: dac900u-etched.step / dac900u-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac900u.step / dac900u.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 bfac39a60981286a, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF