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DAC8802IPWR

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Texas Instruments Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersdac8802ipwrfactory-2.0.0extractor-text

Verified DAC8802IPWR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC8802IPWR · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C2679862, digikey 296-DAC8802IPWRTR-ND, mouser 595-DAC8802IPWR
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-hgw1exbf/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.21)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dac8802ipwr.kicad_sym✓ dac8802ipwr.kicad_mod✓ dac8802ipwr.step
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Ray Publish 0.1.0 6b68250

DAC8802IPWR

Texas Instruments · Digital To Analog Converters (DACs) · TSSOP-16

DAC8802IPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RFBA passive Establishes voltage output for DAC A by connecting to the external amplifier output.
2 VREFA input DAC A reference voltage input terminal that establishes DAC A full-scale output voltage; range -15 V to 15 V and can be tied to the VDD pin.
3 IOUTA output DAC A current output.
4 AGNDA power_in DAC A analog ground.
5 AGNDB power_in DAC B analog ground.
6 IOUTB output DAC B current output.
7 VREFB input DAC B reference voltage input terminal that establishes DAC B full-scale output voltage; range -15 V to 15 V and can be tied to the VDD pin.
8 RFBB passive Establishes voltage output for DAC B by connecting to the external amplifier output.
9 SDI input Serial data input; data loads directly into the shift register.
10 RS input Active-low reset input that sets input and DAC registers to 0x0000 when MSB = 0 or 0x2000 when MSB = 1.
11 CS input Active-low chip select that disables shift register loading when high and transfers serial register data to the input register when CS goes high; does not affect LDAC operation.
12 DGND power_in Digital ground.
13 VDD power_in Positive power-supply input with a specified operating range of 2.7 V to 5.5 V.
14 MSB input Sets output to zero scale (MSB = 0) or midscale (MSB = 1) during a RS pulse or at power-on; can be permanently tied to ground or VDD.
15 LDAC input Level-sensitive active-low asynchronous load DAC register strobe that transfers all input register data to the DAC registers.
16 CLK input Clock input; positive edge clocks data into the shift register.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Data Converters
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative accuracy INL -1 1 LSB 3
Differential nonlinearity DNL -1 1 LSB 3
Output leakage current IOUTX 10 nA Data = 0000h, TA = 25°C 3
Output leakage current IOUTX 20 nA Data = 0000h, TA = TA max 3
Full-scale gain error GFSE 0.75 4 mV Data = 3FFFh 3
Input resistance RREFX 4 5 6 kΩ 3
VREFX Range VREFX -15 15 V 3
Input resistance match RREFX 1 % Channel-to-channel 3
Output current IOUTX 1.6 2.5 mA Data = 3FFFh 3
Input low voltage VIL 0.6 V VDD = 2.7 V 3
Input low voltage VIL 0.8 V VDD = 5 V 3
Input high voltage VIH 2.1 V VDD = 2.7 V 3
Input high voltage VIH 2.4 V VDD = 5 V 3
Input leakage current IIL 1 µA 3
Clock width high tCH 10 ns 3
Clock width low tCL 10 ns 3
CS to Clock setup tCSS 0 ns 3
Clock to CS hold tCSH 10 ns 3
Clock to SDO prop delay tPD 2 20 ns 3
Load DAC pulsewidth tLDAC 20 ns 3
Data setup tDS 10 ns 3
Data hold tDH 10 ns 3
Load setup tLDS 5 ns 3
Load hold tLDH 25 ns 3
Power supply range VDD RANGE 2.7 5.5 V 4
Positive supply current IDD 2 5 µA Logic inputs = 0 V, VDD = 4.5 V to 5.5 V 4
Positive supply current IDD 1 2.5 µA Logic inputs = 0 V, VDD = 2.7 V to 3.6 V 4
VDD to GND VDD -0.3 7 V 2
VREFX, RFBX to GND VREFX, RFBX -18 18 V 2
V(IOUT) to GND V(IOUT) -0.3 V -0.3 to VDD + 0.3 V 2
AGNDX to DGND -0.3 0.3 V 2
Input current to any pin except supplies -50 50 mA 2
Maximum junction temperature TJmax 150 °C 2
Operating temperature range -40 85 °C 2
Storage temperature range -65 150 °C 2
ESD HBM HBM 4 kV 2
ESD CDM CDM 1 kV 2
Thermal resistance, junction to ambient θJA 100 °C/W 2
Resolution 14 Bits 3
Full-scale tempco TCVFS 1 ppm/°C 3
Feedback resistor RFBX 5 kΩ VDD = 5 V 3
Input capacitance CREFX 5 pF 3
Output capacitance COUTX 50 pF Code-dependent 3
Input capacitance CIL 10 pF 3
Power dissipation PDISS 0.0275 mW Logic inputs = 0 V 4
Power supply sensitivity PSS 0.006 % ∆VDD = ±5% 4
Output voltage settling time ts 0.3 µs To ±0.1% of full-scale, Data = 0000h to 3FFFh to 0000h 4
Output voltage settling time ts 0.5 µs To ±0.006% of full-scale, Data = 0000h to 3FFFh to 0000h 4
Reference multiplying BW BW 10 MHz -3 dB VREFX = 100 mVRMS, Data = 3FFFh, CFB = 3 pF 4
Total harmonic distortion THD -105 dB VREF = 5 VPP, Data = 3FFFh, f = 1 kHz 4
Output spot noise voltage en 12 nV/√Hz f = 1 kHz, BW = 1 Hz 4

CAD (KiCad official)

  • Symbol: DAC8802IPWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: dac8802ipwr-etched.step / dac8802ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac8802ipwr.step / dac8802ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 48efe957b70bff37, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF